From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S969590AbdIZOXw (ORCPT ); Tue, 26 Sep 2017 10:23:52 -0400 Received: from smtp-out4.electric.net ([192.162.216.186]:63777 "EHLO smtp-out4.electric.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S969571AbdIZOXv (ORCPT ); Tue, 26 Sep 2017 10:23:51 -0400 From: David Laight To: "'Matt Redfearn'" , David Miller CC: "netdev@vger.kernel.org" , "alexandre.torgue@st.com" , "peppe.cavallaro@st.com" , "linux-kernel@vger.kernel.org" , Linux MIPS Mailing List , Paul Burton , "James Hogan" Subject: RE: [PATCH] net: stmmac: Meet alignment requirements for DMA Thread-Topic: [PATCH] net: stmmac: Meet alignment requirements for DMA Thread-Index: AQHTNs9za6qdFbduzEmZHg5agQgOi6LHNvIw Date: Tue, 26 Sep 2017 14:23:40 +0000 Message-ID: <063D6719AE5E284EB5DD2968C1650D6DD0081391@AcuExch.aculab.com> References: <1506078833-14002-1-git-send-email-matt.redfearn@imgtec.com> <20170922.182639.272534775457081015.davem@davemloft.net> <587dc9a8-b974-e222-95b4-93c2a8f2aba2@imgtec.com> In-Reply-To: <587dc9a8-b974-e222-95b4-93c2a8f2aba2@imgtec.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.99.200] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-Outbound-IP: 156.67.243.126 X-Env-From: David.Laight@ACULAB.COM X-Proto: esmtps X-Revdns: X-HELO: AcuExch.aculab.com X-TLS: TLSv1:AES128-SHA:128 X-Authenticated_ID: X-PolicySMART: 3396946, 3397078 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v8QEOIlx019013 From: Matt Redfearn > Sent: 26 September 2017 14:58 ... > > As long as you use the dma_{map,unamp}_single() and sync to/from > > deivce interfaces properly, the cacheline issues will be handled properly > > and the cpu and the device will see proper uptodate memory contents. > > I interpret the DMA API document (and the MIPS arch dma code operates > this way) as stating that the driver must ensure that buffers passed to > it are cacheline aligned, and cacheline sized, to prevent cache > management throwing away adjacent data in the same cacheline. The important thing is that the driver must not dirty any cache lines that are mapped for DMA (from the device). Typically this is not a problem because the driver doesn't look at skb (etc) that contain receive buffers once the dma is setup. David