From: <Varshini.Rajendran@microchip.com>
To: <claudiu.beznea@tuxon.dev>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <Nicolas.Ferre@microchip.com>,
<alexandre.belloni@bootlin.com>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <Patrice.Vilchez@microchip.com>
Subject: Re: [PATCH] clk: at91: sam9x7: update pll clk ranges
Date: Tue, 24 Jun 2025 09:09:20 +0000 [thread overview]
Message-ID: <0652df01-13e8-4fb8-a2e0-35820d83ac3d@microchip.com> (raw)
In-Reply-To: <c51b2b64-24a7-4e14-bdd8-c4a356423100@tuxon.dev>
Hi Claudiu,
On 24/06/25 12:34 pm, Claudiu Beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi, Varshini,
>
> On 10.06.2025 11:45, Varshini Rajendran wrote:
>> Update the min, max ranges of the PLL clocks according to the latest
>> datasheet to be coherent in the driver. This patch apparently solves
>> issues in obtaining the right sdio frequency.
>>
>> Fixes: 33013b43e271 ("clk: at91: sam9x7: add sam9x7 pmc driver")
>> Suggested-by: Patrice Vilchez <Patrice.Vilchez@microchip.com>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> drivers/clk/at91/sam9x7.c | 20 ++++++++++----------
>> 1 file changed, 10 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
>> index cbb8b220f16b..ffab32b047a0 100644
>> --- a/drivers/clk/at91/sam9x7.c
>> +++ b/drivers/clk/at91/sam9x7.c
>> @@ -61,44 +61,44 @@ static const struct clk_master_layout sam9x7_master_layout = {
>>
>> /* Fractional PLL core output range. */
>> static const struct clk_range plla_core_outputs[] = {
>> - { .min = 375000000, .max = 1600000000 },
>> + { .min = 800000000, .max = 1600000000 },
>> };
>>
>> static const struct clk_range upll_core_outputs[] = {
>> - { .min = 600000000, .max = 1200000000 },
>> + { .min = 600000000, .max = 960000000 },
>> };
>>
>> static const struct clk_range lvdspll_core_outputs[] = {
>> - { .min = 400000000, .max = 800000000 },
>> + { .min = 600000000, .max = 1200000000 },
>> };
>>
>> static const struct clk_range audiopll_core_outputs[] = {
>> - { .min = 400000000, .max = 800000000 },
>> + { .min = 600000000, .max = 1200000000 },
>> };
>>
>> static const struct clk_range plladiv2_core_outputs[] = {
>> - { .min = 375000000, .max = 1600000000 },
>> + { .min = 800000000, .max = 1600000000 },
>> };
>>
>> /* Fractional PLL output range. */
>> static const struct clk_range plla_outputs[] = {
>> - { .min = 732421, .max = 800000000 },
>> + { .min = 400000000, .max = 800000000 },
>> };
>>
>> static const struct clk_range upll_outputs[] = {
>> - { .min = 300000000, .max = 600000000 },
>> + { .min = 300000000, .max = 480000000 },
>> };
>>
>> static const struct clk_range lvdspll_outputs[] = {
>> - { .min = 10000000, .max = 800000000 },
>> + { .min = 175000000, .max = 550000000 },
>> };
>>
>> static const struct clk_range audiopll_outputs[] = {
>> - { .min = 10000000, .max = 800000000 },
>> + { .min = 0, .max = 300000000 },
>
> Is this min value something valid?
Yes. This is a valid value mentioned in the datasheet. This is the range
that fixes the issue of not being able to set low frequency values for
the SDIO interface for instance.
>
> Thank you,
> Claudiu
--
Thanks and Regards,
Varshini Rajendran.
next prev parent reply other threads:[~2025-06-24 9:09 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-10 8:45 Varshini Rajendran
2025-06-24 7:04 ` Claudiu Beznea
2025-06-24 9:09 ` Varshini.Rajendran [this message]
2025-07-10 8:18 ` Claudiu Beznea
2025-07-11 7:38 ` Varshini.Rajendran
2025-07-11 12:58 ` Claudiu Beznea
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