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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ba4520ca202sm1103240266b.28.2026.04.27.07.45.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Apr 2026 07:45:29 -0700 (PDT) Message-ID: <06cef5c0-3473-4e3a-81f2-37a41216f67a@oss.qualcomm.com> Date: Mon, 27 Apr 2026 16:45:26 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/6] arm64: dts: qcom: Add AYN QCS8550 Common To: Aaron Kling Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Teguh Sobirin References: <20260408-ayn-qcs8550-v5-0-c90abeb7a152@gmail.com> <20260408-ayn-qcs8550-v5-3-c90abeb7a152@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: iDGaBoxe18hTIPMh0WS7TTAnMoTkjYSd X-Authority-Analysis: v=2.4 cv=Xba5Co55 c=1 sm=1 tr=0 ts=69ef768c cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=UM7KGhH_uoedJeHknsEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: iDGaBoxe18hTIPMh0WS7TTAnMoTkjYSd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI3MDE1NiBTYWx0ZWRfX8bIfv685RFuM 2I7NcStRbks060HfYxWooDVpuSdGZ3e9uZQX7qjQYJD/YuEcMLrKbCs/qm45XibxytgeZ9zX1f6 6CoyzXeVhzukXgFD+m7si0RgpnLIC8I9U+3EaBWd2k9AsNIH3bryfZnhRFlAn199kKhjSVxRrRG WpGTO/nUSXpQ2jxXFhQO3Yoo1bnWo94BBMlzveKuxZXy3IDdTapNPpNbXfyIJYdW0xVbAy/uR9A M3aDnKSTmH0PTvBxvhk8y9kU/QHDX0UJwWHSXYvhBj76tio6pi2XQ4fZRAb8bTyOSDJj1/bzqRB lGtvGFA27oqGd0ke3EhtcjUnbNbK6JH0UHboUTrk75ukyuv4iweaOlN6XvF1I7oOsreYCGxWNv/ u1XvuEb2nbmltXCmKcRjWPCbRPE94NuKzNGyW9fZmtaUS2IIorlDAuP5bLouY+6/yW1x8mZaVXX xiXZXrdyRtgPX1N4yHQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-27_04,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270156 On 4/27/26 12:01 AM, Aaron Kling wrote: > On Fri, Apr 24, 2026 at 7:11 AM Konrad Dybcio > wrote: >> >> On 4/8/26 9:41 PM, Aaron Kling via B4 Relay wrote: >>> From: Teguh Sobirin >>> >>> This contains everything common between the AYN QCS8550 devices. It will >>> be included by device specific dts'. >>> >>> Signed-off-by: Teguh Sobirin >>> Co-developed-by: Aaron Kling >>> Signed-off-by: Aaron Kling >>> --- [...] >>> +&pm8550_gpios { >>> + fan_pwm_active: fan-pwm-active-state { >>> + pins = "gpio8"; >>> + function = "func1"; >>> + input-disable; >>> + output-enable; >>> + output-low; >> >> Looks like this should be a regulator then, probably? > > Mmm, what would it be tied to, then? The fan already has a reg. I > presume just modeling it as an always on reg tied to nothing is > undesirable. I also have no idea what the voltage would be. Or maybe it's some sort of reset/enable GPIO. Or an enable pin to whatever feeds into VDD_FAN_5V0. It's hard to tell indeed. > >> [...] >> >>> + wcd_default: wcd-reset-n-active-state { >>> + pins = "gpio108"; >>> + function = "gpio"; >>> + drive-strength = <16>; >>> + bias-disable; >>> + output-low; >> >> no need for this property > > I'll start with saying that I know basically nothing about qcom > hardware design and what the average pinmuxing layout looks like. But > I do note that a lot of existing devices have this exact same node, > for example the sm8550 hdk [0]. Is there something that makes these > devices different? Or is this unnecessary everywhere? That's my understanding. [...] >>> + usb0_sbu_default: usb0-sbu-state { >>> + oe-n-pins { >>> + pins = "gpio140"; >>> + function = "gpio"; >>> + bias-disable; >>> + drive-strength = <16>; >>> + output-high; >> >> This is probably not required too.. unless there's a hw bug? >> >> fwiw 16 mA is a very high drive-strength - does this come from vendor >> sources? > > I do not see any pinmux for gpio140 in the downstream dt or anything > matching pi3usb102 at all, I'm not sure how it's handled there. The > original source of this dt was written before there was a public gpl > code release from AYN. I do see other qcom users of the pi3usb102 > doing similar however, for example the sc8280xp crd [1]. So I've got > the same question as above: is there something different here, or is > it possible other existing copies of this are also wrong? You can retrieve the settings from your device at runtime, /sys/kernel/debug/gpio will read back the hw settings As for the CRD, I don't know. It may as well be board-specific. Konrad