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Tue, 10 Dec 2024 07:56:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IGO/en2fuAvQyTs2jHHMl4LqDZEtajqMB/Su9iQAs0bW7stQDAwQKFTzGD6u5DQDQ+uVMvWSg== X-Received: by 2002:a05:6602:a108:b0:83a:943d:a280 with SMTP id ca18e2360f4ac-844b87f7863mr299997739f.1.1733846207687; Tue, 10 Dec 2024 07:56:47 -0800 (PST) Received: from [192.168.40.164] ([70.105.235.240]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4e2bf67d125sm1155622173.96.2024.12.10.07.56.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Dec 2024 07:56:47 -0800 (PST) Message-ID: <0723d890-1f90-463b-a814-9f7bb7e2200b@redhat.com> Date: Tue, 10 Dec 2024 10:56:43 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/1] KVM: arm64: Map GPU memory with no struct pages Content-Language: en-US To: Jason Gunthorpe , Will Deacon Cc: ankita@nvidia.com, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, ryan.roberts@arm.com, shahuang@redhat.com, lpieralisi@kernel.org, aniketa@nvidia.com, cjia@nvidia.com, kwankhede@nvidia.com, targupta@nvidia.com, vsethi@nvidia.com, acurrid@nvidia.com, apopple@nvidia.com, jhubbard@nvidia.com, danw@nvidia.com, zhiw@nvidia.com, mochs@nvidia.com, udhoke@nvidia.com, dnigam@nvidia.com, alex.williamson@redhat.com, sebastianene@google.com, coltonlewis@google.com, kevin.tian@intel.com, yi.l.liu@intel.com, ardb@kernel.org, akpm@linux-foundation.org, gshan@redhat.com, linux-mm@kvack.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20241118131958.4609-1-ankita@nvidia.com> <20241210140739.GC15607@willie-the-truck> <20241210141806.GI2347147@nvidia.com> From: Donald Dutile In-Reply-To: <20241210141806.GI2347147@nvidia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/10/24 9:18 AM, Jason Gunthorpe wrote: > On Tue, Dec 10, 2024 at 02:07:40PM +0000, Will Deacon wrote: >> On Mon, Nov 18, 2024 at 01:19:57PM +0000, ankita@nvidia.com wrote: >>> The changes are heavily influenced by the insightful discussions between >>> Catalin Marinas and Jason Gunthorpe [1] on v1. Many thanks for their >>> valuable suggestions. >>> >>> Link: https://lore.kernel.org/lkml/20230907181459.18145-2-ankita@nvidia.com [1] >> >> That's a different series, no? It got merged at v9: > > I was confused by this too. v1 of that series included this patch, as > that series went along it became focused only on enabling WC > (Normal-NC) in a VM for device MMIO and this patch for device cachable > memory was dropped off. > > There are two related things: > 1) Device MMIO memory should be able to be Normal-NC in a VM. Already > merged > 2) Device Cachable memory (ie CXL and pre-CXL coherently attached > memory) should be Normal Cachable in a VM, even if it doesn't have > struct page/etc. (this patch) > > IIRC this part was dropped off because of the MTE complexity that > Catalin raised. > > Jason > Jason & Catalin: Thanks for the filler for the splitting. So, I'm not sure I read what is needed to resolve this patch. I read Will's reply to split it further and basically along what logical lines of functionality; is there still an MTE complexity that has to be resolved/included in the series? IOW, I'm looking for a complete, clear (set of) statement(s) that Ankit can implement to get this (requested) series moving forward, sooner than later; it's already been a year+ to get to this point, and I don't want further ambiguity/uncertainty to drag it out more than needed. Thanks... Don