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Fri, 21 Aug 2026 15:06:15 -0700 (PDT) Message-ID: <072f26a26bbba19cf8701472141590ffadd72f45.camel@redhat.com> Subject: Re: [PATCH v2 07/10] drm/nouveau/disp: fix head state readback on GB20x From: lyude@redhat.com To: Mohamed Ahmed , linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard , nouveau@lists.freedesktop.org Date: Fri, 21 Aug 2026 18:06:14 -0400 In-Reply-To: <20260820164929.17117-8-mohamedahmedegypt2001@gmail.com> References: <20260820164929.17117-1-mohamedahmedegypt2001@gmail.com> <20260820164929.17117-8-mohamedahmedegypt2001@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 (3.58.3-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 One nitpick below On Thu, 2026-08-20 at 20:49 +0400, Mohamed Ahmed wrote: > The GSP path reads armed head state and the RG scanout position > through > gv100_head_state() and gv100_head_rgpos() on every generation. > gv100_head_state() reads the core channel's state mirror at a 0x400 > per-head stride, which NVD5.0 (GB20x) doubled. Per NVIDIA's published > CA7D class header every HEAD_SET method sits at 0x2000 + head * > 0x800, > while the mirror bases are unchanged (assembly at 0x680000, armed at > +0x8000, per OpenRM's v03_00 channel-user-base HAL which is still > used on > DISPv0502). >=20 > Add gb202_head_state(), the same readback at the 0x800 stride, and > supply it through gb202_gsp_disp. > gv100_head_rgpos() is kept. The RG registers keep their per-head > 0x800 > stride on NVD5.0, and OpenRM's > kdispReadRgLineCountAndFrameCount_v03_00 > still reads NV_PDISP_RG_DPCA on DISPv0502. >=20 > Signed-off-by: Mohamed Ahmed > --- > =C2=A0.../gpu/drm/nouveau/nvkm/engine/disp/gb202.c=C2=A0 | 49 > ++++++++++++++++++- > =C2=A01 file changed, 48 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c > b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c > index 4863b2b36db0..a66c820be9fe 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c > @@ -83,6 +83,53 @@ gb202_sor_hdmi_gcp(struct nvkm_ior *sor, int head, > bool enable) > =C2=A0 nvkm_mask(device, 0x6f0040 + hdmi, 0x00000001, 0x00000001); > =C2=A0} > =C2=A0 > +/* Same core-channel state mirror as gv100_head_state() (assembly at > 0x680000, > + * armed at +0x8000, per-head method offsets unchanged), but NVD5.0 > spaces > + * heads 0x800 apart (see NVCA7D_HEAD_SET_*(a) in clca7d.h). > + */ > +static void > +gb202_head_state(struct nvkm_head *head, struct nvkm_head_state > *state) > +{ > + struct nvkm_device *device =3D head->disp- > >engine.subdev.device; > + const u32 hoff =3D (state =3D=3D &head->arm) * 0x8000 + head->id * > 0x800; > + u32 data; > + > + data =3D nvkm_rd32(device, 0x682064 + hoff); > + state->vtotal =3D (data & 0xffff0000) >> 16; > + state->htotal =3D (data & 0x0000ffff); > + data =3D nvkm_rd32(device, 0x682068 + hoff); > + state->vsynce =3D (data & 0xffff0000) >> 16; > + state->hsynce =3D (data & 0x0000ffff); > + data =3D nvkm_rd32(device, 0x68206c + hoff); > + state->vblanke =3D (data & 0xffff0000) >> 16; > + state->hblanke =3D (data & 0x0000ffff); > + data =3D nvkm_rd32(device, 0x682070 + hoff); > + state->vblanks =3D (data & 0xffff0000) >> 16; > + state->hblanks =3D (data & 0x0000ffff); > + /* Bit 31 is ADJ1000DIV1001, not a HERTZ bit. We don't have > enough bits > + * to add the full clock in hz on Blackwell (35 bits), but > state->hz > + * is unused and obsolete under GSP so this is fine. > + */ > + state->hz =3D nvkm_rd32(device, 0x68200c + hoff) & 0x7fffffff; > + > + data =3D nvkm_rd32(device, 0x682004 + hoff); > + switch ((data & 0x000000f0) >> 4) { > + case 5: > + state->or.depth =3D 30; > + break; > + case 4: > + state->or.depth =3D 24; > + break; > + case 1: > + state->or.depth =3D 18; > + break; > + default: > + state->or.depth =3D 18; > + WARN_ON(1); > + break; > + } I would probably condense this switch case like ben did with gv100_head_state(): switch ((data & 0x000000f0) >> 4) { case 5: state->or.depth =3D 30; break; case 4: state->or.depth =3D 24; break; case 1: state->or.depth =3D 18; break; default: state->or.depth =3D 18; WARN_ON(1); break; } With that fixed: Reviewed-by: Lyude Paul > +} > + > =C2=A0/* GB20x is GSP-only. This table supplies the register programming > the > =C2=A0 * GSP-RM display path needs from the chip. > =C2=A0 */ > @@ -91,7 +138,7 @@ gb202_gsp_disp =3D { > =C2=A0 .uevent =3D &gv100_disp_chan_uevent, > =C2=A0 .ramht_size =3D 0x2000, > =C2=A0 .gsp.intr =3D tu102_disp_intr, > - .gsp.head_state =3D gv100_head_state, > + .gsp.head_state =3D gb202_head_state, > =C2=A0 .gsp.head_rgpos =3D gv100_head_rgpos, > =C2=A0 .gsp.vblank_get =3D tu102_head_vblank_get, > =C2=A0 .gsp.vblank_put =3D tu102_head_vblank_put,