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Thu, 22 Apr 2021 08:15:37 +0000 Received: from [10.26.49.10] (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Apr 2021 08:15:33 +0000 Subject: Re: [PATCH tip 1/2] signal, perf: Fix siginfo_t by avoiding u64 on 32-bit architectures To: Marco Elver , , , CC: , , , , , , , , , , , References: <20210422064437.3577327-1-elver@google.com> From: Jon Hunter Message-ID: <0734b0e8-b4c0-05bb-b90c-de89edb61b5d@nvidia.com> Date: Thu, 22 Apr 2021 09:15:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <20210422064437.3577327-1-elver@google.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9d710e30-c035-4cad-4b5a-08d90566cf64 X-MS-TrafficTypeDiagnostic: DM6PR12MB4548: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2021 08:15:37.2796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d710e30-c035-4cad-4b5a-08d90566cf64 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4548 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/04/2021 07:44, Marco Elver wrote: > On some architectures, like Arm, the alignment of a structure is that of > its largest member. > > This means that there is no portable way to add 64-bit integers to > siginfo_t on 32-bit architectures, because siginfo_t does not contain > any 64-bit integers on 32-bit architectures. > > In the case of the si_perf field, word size is sufficient since there is > no exact requirement on size, given the data it contains is user-defined > via perf_event_attr::sig_data. On 32-bit architectures, any excess bits > of perf_event_attr::sig_data will therefore be truncated when copying > into si_perf. > > Since this field is intended to disambiguate events (e.g. encoding > relevant information if there are more events of the same type), 32 bits > should provide enough entropy to do so on 32-bit architectures. > > For 64-bit architectures, no change is intended. > > Fixes: fb6cc127e0b6 ("signal: Introduce TRAP_PERF si_code and si_perf to siginfo") > Reported-by: Marek Szyprowski > Tested-by: Marek Szyprowski > Reported-by: Jon Hunter > Signed-off-by: Marco Elver Thanks for fixing! Tested-by: Jon Hunter Cheers Jon -- nvpublic