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Fri, 04 Oct 2024 08:01:19 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 494817jW001230 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 08:01:07 GMT Received: from [10.50.18.17] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 01:01:00 -0700 Message-ID: <07467780-c84a-442d-b4b8-a96a5c2630eb@quicinc.com> Date: Fri, 4 Oct 2024 13:30:57 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V5 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node To: Dmitry Baryshkov , Devi Priya CC: , , , , , , , , , , , , , , , , , , , , , , References: <20240626143302.810632-1-quic_devipriy@quicinc.com> <20240626143302.810632-7-quic_devipriy@quicinc.com> Content-Language: en-US From: Manikanta Mylavarapu In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: d9G4Xr5LXwXbFKHQEb9M3ydj8pWsV4TV X-Proofpoint-ORIG-GUID: d9G4Xr5LXwXbFKHQEb9M3ydj8pWsV4TV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040057 On 6/26/2024 11:43 PM, Dmitry Baryshkov wrote: > On Wed, Jun 26, 2024 at 08:03:01PM GMT, Devi Priya wrote: >> Add a node for the nss clock controller found on ipq9574 based devices. >> >> Signed-off-by: Devi Priya >> --- >> Changes in V5: >> - Dropped interconnects from nsscc node and added >> interconnect-cells to NSS clock provider so that it can be used >> as icc provider. >> >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 41 +++++++++++++++++++++++++++ >> 1 file changed, 41 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 48dfafea46a7..b6f8800bf63c 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -11,6 +11,8 @@ >> #include >> #include >> #include >> +#include >> +#include >> #include >> >> / { >> @@ -19,6 +21,24 @@ / { >> #size-cells = <2>; >> >> clocks { >> + bias_pll_cc_clk: bias-pll-cc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1200000000>; >> + #clock-cells = <0>; >> + }; >> + >> + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <461500000>; >> + #clock-cells = <0>; >> + }; >> + >> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <353000000>; >> + #clock-cells = <0>; >> + }; > > What is the source for these clocks? Is it really an on-board crystal? > Hi Dmitry, Sorry for the delayed response. No, the CMN PLL [1] is the source for these clocks. Will remove these nodes and set these entries to 0 in the nsscc node until the CMN PLL driver posted with these clocks. 1: https://lore.kernel.org/lkml/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com/ Thanks & Regards, Manikanta.