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Tue, 13 Oct 2026 00:34:01 -0700 (PDT) X-Received: by 2002:a17:90b:4fcb:b0:3a4:bbec:b4b4 with SMTP id 98e67ed59e1d1-3ab3a94c1efmr9124362a91.26.1791876840939; Tue, 13 Oct 2026 00:34:00 -0700 (PDT) Received: from [10.204.78.62] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ab371e2833sm20926517a91.17.2026.10.13.00.33.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Oct 2026 00:34:00 -0700 (PDT) Message-ID: <0752c7fd-4746-4260-bc24-3e8785bc936f@oss.qualcomm.com> Date: Tue, 13 Oct 2026 13:03:54 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/6] drm/msm/dpu: rework layer mixer allocation and mode limits To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Xilin Wu , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20261008-lm_fixes_final-v4-0-fa986071c3c1@oss.qualcomm.com> Content-Language: en-US From: Mahadevan P In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: MpYhIVPM0m6vqCuW6Hnyio-bq75wQTm1 X-Authority-Analysis: v=2.4 cv=FZuiV5+6 c=1 sm=1 tr=0 ts=6acddeea cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=z6WxN8cy-vpheZIcWT4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEzMDAyOSBTYWx0ZWRfX4/Hp0gRKDlTV /EKAKP0a3NJtPAZKVwV6FBdMORH47J2bakN7oBE3nlVxTUvIA3HhR9M1xUKRqbDui+BMC8Ng4yj GgLb5meAqH//VVYE0E8sul7SdX+Ra8c= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEzMDAyOSBTYWx0ZWRfXz8iZ2KSfXSLk 2KoB1TIu8HCAkWOXSvCJNzHTjLHLe/IWznNddjutviO2Q5kC5vLomqs11sMLVY1/Pz7L9sv0zSv LFXE3fe6IjMcA4EUR0mtNfoVrN1aamFZ95is1oFF3PfmuZHWl9c9Xsz0dXlZ0rSS2AWuww/NcTA Bjji7RHzCls4B9AYRO9smS82rDt/FLI9BDyG51Ak16wDsrwy2I6BvmwXIGsXArtbcHzhWaJd6iT stqsL91qUeW3SYbA/xhu6IWuIekd+UhGvDgS8BXzMmhJx0ycARDYXsrZXnXzvgBFnJrfxiCte3h O2ki/xs4xD4TltKN1irHbpOYqu2A2yLE65FBp9k+32ENbZ9Y1f2cnstUPDUsqvub+IbxidgDbX7 z/6eH7ACRH7fPNzraKvXDATY9ORtehj6wCRpdeqV0nSk929A0fMRHPU13KnHxq6GADW+O7T9Die qsb+72kbJaykwGkCA+w== X-Proofpoint-ORIG-GUID: MpYhIVPM0m6vqCuW6Hnyio-bq75wQTm1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610130029 On 10/12/2026 5:35 PM, Dmitry Baryshkov wrote: > On Thu, Oct 08, 2026 at 10:53:46PM +0530, Mahadevan P wrote: >> Currently, the DPU driver bases LM reservation off of the maximum >> supported width for the layer mixer and an arbitrary MAX_HDISPLAY_SPLIT. >> However, these limits are not hardware limits meaning that a single LM >> can support higher resolutions. >> >> Switch to basing LM reservation off of PINGPONG and DSC encoder hardware >> limits. >> >> This revision also adds clock-based mixer selection and a source-pipe >> width guard for mixers without source split. >> >> Assisted-by: LLM >> Signed-off-by: Mahadevan P >> --- >> Changes in v4: >> - Rebased on msm-next, resolving conflicts. >> - Added clock-based mixer selection and reused the helper in mode >> validation. >> - Added a source-pipe width guard for mixers without source split. >> - Extended the catalog cleanup to newer platforms. > What was the issue that caused display breakage on the CRD as reported > by Xilin Wu? How did you fix it? The v3 change allowed this mode to use one LM because its width fits within the PINGPONG limit, without accounting for LM throughput. For the reported 3840×2160@120 timing, a single LM requires 1036.8 MHz before margin, exceeding the reported 600 MHz MDP clock. v4 adds clock-based LM selection, retaining two LMs for this mode and addressing the allocation issue. The separate clock-validation requirement remains: the dual-pipe rate is 1188 / 2 = 594 MHz, increasing to 623.7 MHz with the 5% inefficiency margin specified by the HPG. Xilin’s working test bypassed that check. At 600 MHz, there is only about 1% headroom above 594 MHz, so success in that configuration does not guarantee reliable operation across other workloads, where underruns may still occur. We therefore cannot remove the hardware programming guide prescribed 5% margin based on this test alone. Thanks, Mahadevan > >> - Link to v3: https://lore.kernel.org/r/20260112-max-mixer-width-v3-0-f98063ea21f5@oss.qualcomm.com >>