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Tue, 11 Aug 2026 07:00:43 -0700 (PDT) X-Received: by 2002:a17:903:2308:b0:2c8:1f58:55dd with SMTP id d9443c01a7336-2d32bfc5a1amr8916675ad.9.1786456841948; Tue, 11 Aug 2026 07:00:41 -0700 (PDT) Received: from [192.168.1.9] ([122.164.84.216]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d315f458casm8834495ad.33.2026.08.11.07.00.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Aug 2026 07:00:41 -0700 (PDT) Message-ID: <076b0942-7e1a-4a6c-9293-04a7ff77abcb@oss.qualcomm.com> Date: Tue, 11 Aug 2026 19:30:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus To: Luo Jie , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260811-qcom_ipq5018_mdio_pinctrl-v1-1-14ae9dc62a3f@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <20260811-qcom_ipq5018_mdio_pinctrl-v1-1-14ae9dc62a3f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: zi06KdPNpB3cb2RXreMLNndXTsxVjFXA X-Authority-Analysis: v=2.4 cv=IO4yzAvG c=1 sm=1 tr=0 ts=6a7b2b0b cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=0/lRlipvHLU+ZVN6ZkkSUA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=2y_uGkg87WrGdd1x8YcA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODExMDExNiBTYWx0ZWRfX2vrcME79UwIZ bVOoqoMFsShOcMPGxrv7FFZWvdR6BRbs8mnFjMCIAmVq+fnfZ9StKE6Ur6ceOhqEUGtSxwPnNbM B05xbWDvf9eYbSEwjaYH7ZLWE8eUL/VEHsSgcGVKBmJU0F/2WR9fNQ8KpS4obXQ1H3JGXEORIXd 24JQuUk3WlbZJM2dDYGbm8iaudNtqVnBQwwvqltswzB3ZYQEC3u5LBaEX9FkGIBvwVIF4HWOjWw P2a2xgw7imtQcFDtkkEGosI3yBnq0OCmOiDfdtYlmZaVJnq1a0OKKk2wYaGRt2zPORcS9YxXc39 LrMEsv52HKEsuH5/4vcJ/2RevaAsJltdPLCQjSkXjk8adVRHIzZudamBx9b0WwJ+jINi7e6GOEt OjcUlaHLCbSQiFv1ejHAp4neyhFquchhkpOC49Em0E7wRu8Jklf4U7urG2ayQqZ2gLpXcIH4jwd l1x1rv4FtkuCz5NFTGg== X-Proofpoint-GUID: zi06KdPNpB3cb2RXreMLNndXTsxVjFXA X-Proofpoint-Spam-Info: AW1haW4tMjYwODExMDExNiBTYWx0ZWRfX5TVTuuvlA4vY Od8Bz1xSf7NWF4bWhdDJH9ARY+vpaiP2KXwMHVFnxMqV3lIADTE4G9xfKxDRZeyobY9q2ejU+b0 NH9uETvNU83/HXmyfOkJ2lSj6PcU6t0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-11_03,2026-08-10_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608110116 On 8/11/2026 7:06 PM, Luo Jie wrote: > The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via > TLMM pinctrl; without this the pins are left in their default state and > the bus does not function on boards that enable it. Should we move the TLMM definitions to the board DTS file rather than keeping it in the SoC DTSI? > > Add a mdio_pins pinctrl state for gpio36 (mdc) and gpio37 (mdio) with > 8mA drive strength and pull-up, and reference it from the mdio1 node > via pinctrl-0/pinctrl-names. > > Signed-off-by: Luo Jie > --- > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi > index 4fc627b47fe7..a8a89a9c8160 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi > @@ -241,6 +241,8 @@ mdio1: mdio@90000 { > reg = <0x00090000 0x64>; > #address-cells = <1>; > #size-cells = <0>; > + pinctrl-0 = <&mdio_pins>; > + pinctrl-names = "default"; > > clocks = <&gcc GCC_MDIO1_AHB_CLK>; > clock-names = "gcc_mdio_ahb_clk"; > @@ -427,6 +429,22 @@ uart1_pins: uart1-state { > drive-strength = <8>; > bias-pull-down; > }; > + > + mdio_pins: mdio-state { > + mdc-pins { > + pins = "gpio36"; > + function = "mdc"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + > + mdio-pins { > + pins = "gpio37"; > + function = "mdio"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > }; > > gcc: clock-controller@1800000 { > > --- > base-commit: 3d08ff75a47a3e7e2ab45a3bcab6723b4d906422 > change-id: 20260811-qcom_ipq5018_mdio_pinctrl-f9e609e97c3d > > Best regards, > -- > Luo Jie > >