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([2a01:e0a:982:cbb0:c5bb:5b4:61e3:d196]) by smtp.gmail.com with ESMTPSA id c7-20020a7bc847000000b003fe22da3bc5sm1772761wml.42.2023.08.02.07.11.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Aug 2023 07:11:29 -0700 (PDT) Message-ID: <079ece4b-3f36-2ff9-36ff-23fcc4c2c8e1@linaro.org> Date: Wed, 2 Aug 2023 16:11:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH] drm/msm/dpu: increase memtype count to 16 for sm8550 Content-Language: en-US To: Jonathan Marek , freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Konrad Dybcio , Kuogee Hsieh , Robert Foss , Bjorn Andersson , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list References: <20230802134900.30435-1-jonathan@marek.ca> Organization: Linaro Developer Services In-Reply-To: <20230802134900.30435-1-jonathan@marek.ca> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/08/2023 15:48, Jonathan Marek wrote: > sm8550 has 16 vbif clients. > > This fixes the extra 2 clients (DMA4/DMA5) not having their memtype > initialized. This fixes DMA4/DMA5 planes not displaying correctly. > > Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550") > Signed-off-by: Jonathan Marek > --- > .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++++++++++ > 2 files changed, 22 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > index f17b9a7fee85..89a2ac1e840d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > @@ -245,8 +245,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { > .merge_3d = sm8550_merge_3d, > .intf_count = ARRAY_SIZE(sm8550_intf), > .intf = sm8550_intf, > - .vbif_count = ARRAY_SIZE(sdm845_vbif), > - .vbif = sdm845_vbif, > + .vbif_count = ARRAY_SIZE(sm8550_vbif), > + .vbif = sm8550_vbif, > .perf = &sm8550_perf_data, > .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ > BIT(MDP_SSPP_TOP0_INTR2) | \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 0de507d4d7b7..8b17a4a9b438 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -663,6 +663,26 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = { > }, > }; > > +static const struct dpu_vbif_cfg sm8550_vbif[] = { > + { > + .name = "vbif_rt", .id = VBIF_RT, > + .base = 0, .len = 0x1040, > + .features = BIT(DPU_VBIF_QOS_REMAP), > + .xin_halt_timeout = 0x4000, > + .qos_rp_remap_size = 0x40, > + .qos_rt_tbl = { > + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), > + .priority_lvl = sdm845_rt_pri_lvl, > + }, > + .qos_nrt_tbl = { > + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), > + .priority_lvl = sdm845_nrt_pri_lvl, > + }, > + .memtype_count = 16, > + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, > + }, > +}; > + > /************************************************************* > * PERF data config > *************************************************************/ Thanks ! Tested-by: Neil Armstrong # on SM8550-QRD