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charset=utf-8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3774.500.171.1.1\)) Subject: Re: [PATCH V2 7/9] tools/perf: Update instruction tracking with add instruction From: Athira Rajeev In-Reply-To: <7c8af115-56fb-4b1f-818c-f2a7d532166b@csgroup.eu> Date: Thu, 23 May 2024 19:25:55 +0530 Cc: "acme@kernel.org" , "jolsa@kernel.org" , "adrian.hunter@intel.com" , "irogers@google.com" , "namhyung@kernel.org" , "segher@kernel.crashing.org" , "linux-perf-users@vger.kernel.org" , "linuxppc-dev@lists.ozlabs.org" , "maddy@linux.ibm.com" , "kjain@linux.ibm.com" , "disgoel@linux.vnet.ibm.com" , "linux-kernel@vger.kernel.org" , "akanksha@linux.ibm.com" Content-Transfer-Encoding: quoted-printable Message-Id: <07BB6C89-D014-44EF-87A7-42A15C43EDD6@linux.vnet.ibm.com> References: <20240506121906.76639-1-atrajeev@linux.vnet.ibm.com> <20240506121906.76639-8-atrajeev@linux.vnet.ibm.com> <7c8af115-56fb-4b1f-818c-f2a7d532166b@csgroup.eu> To: Christophe Leroy X-Mailer: Apple Mail (2.3774.500.171.1.1) X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: gRgaGV3KD953S74j9LgzaKHKTLDSHr2L X-Proofpoint-GUID: 6dP_0A09OfUJccs6J35rocteLegzsgBW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-23_08,2024-05-23_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405230096 > On 7 May 2024, at 3:28=E2=80=AFPM, Christophe Leroy = wrote: >=20 >=20 >=20 > Le 06/05/2024 =C3=A0 14:19, Athira Rajeev a =C3=A9crit : >> Update instruction tracking with add instruction. Apart from "mr" >> instruction, the register state is carried on by other insns, ie, >> "add, addi, addis". Since these are not memory instructions and = doesn't >> fall in the range of (32 to 63), add these as part of nmemonic table. >> For now, add* instructions are added. There is possibility of getting >> more added here. But to extract regs, still the binary code will be >> used. So associate this with "load_store_ops" itself and no other >> changes required. >=20 > Looks fragile. >=20 > How do you handle addc, adde, addic ? > And also addme, addze, which only have two operands instead of 3 ? Hi Christophe, Thanks for pointing these cases. Will address these cases in next = version Thanks Athira >=20 >>=20 >> Signed-off-by: Athira Rajeev >> --- >> .../perf/arch/powerpc/annotate/instructions.c | 21 = +++++++++++++++++++ >> tools/perf/util/disasm.c | 1 + >> 2 files changed, 22 insertions(+) >>=20 >> diff --git a/tools/perf/arch/powerpc/annotate/instructions.c = b/tools/perf/arch/powerpc/annotate/instructions.c >> index cce7023951fe..1f35d8a65bb4 100644 >> --- a/tools/perf/arch/powerpc/annotate/instructions.c >> +++ b/tools/perf/arch/powerpc/annotate/instructions.c >> @@ -1,6 +1,17 @@ >> // SPDX-License-Identifier: GPL-2.0 >> #include >>=20 >> +/* >> + * powerpc instruction nmemonic table to associate load/store = instructions with >> + * move_ops. mov_ops is used to identify add/mr to do instruction = tracking. >> + */ >> +static struct ins powerpc__instructions[] =3D { >> + { .name =3D "mr", .ops =3D &load_store_ops, }, >> + { .name =3D "addi", .ops =3D &load_store_ops, }, >> + { .name =3D "addis", .ops =3D &load_store_ops, }, >> + { .name =3D "add", .ops =3D &load_store_ops, }, >> +}; >> + >> static struct ins_ops *powerpc__associate_instruction_ops(struct = arch *arch, const char *name) >> { >> int i; >> @@ -75,6 +86,9 @@ static void update_insn_state_powerpc(struct = type_state *state, >> if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0) >> return; >>=20 >> + if (!strncmp(dl->ins.name, "add", 3)) >> + goto regs_check; >> + >> if (strncmp(dl->ins.name, "mr", 2)) >> return; >>=20 >> @@ -85,6 +99,7 @@ static void update_insn_state_powerpc(struct = type_state *state, >> dst->reg1 =3D src_reg; >> } >>=20 >> +regs_check: >> if (!has_reg_type(state, dst->reg1)) >> return; >>=20 >> @@ -115,6 +130,12 @@ static void update_insn_state_powerpc(struct = type_state *state __maybe_unused, s >> static int powerpc__annotate_init(struct arch *arch, char *cpuid = __maybe_unused) >> { >> if (!arch->initialized) { >> + arch->nr_instructions =3D ARRAY_SIZE(powerpc__instructions); >> + arch->instructions =3D calloc(arch->nr_instructions, sizeof(struct = ins)); >> + if (!arch->instructions) >> + return -ENOMEM; >> + memcpy(arch->instructions, powerpc__instructions, sizeof(struct = ins) * arch->nr_instructions); >> + arch->nr_instructions_allocated =3D arch->nr_instructions; >> arch->initialized =3D true; >> arch->associate_instruction_ops =3D = powerpc__associate_instruction_ops; >> arch->objdump.comment_char =3D '#'; >> diff --git a/tools/perf/util/disasm.c b/tools/perf/util/disasm.c >> index ac6b8b8da38a..32cf506a9010 100644 >> --- a/tools/perf/util/disasm.c >> +++ b/tools/perf/util/disasm.c >> @@ -36,6 +36,7 @@ static struct ins_ops mov_ops; >> static struct ins_ops nop_ops; >> static struct ins_ops lock_ops; >> static struct ins_ops ret_ops; >> +static struct ins_ops load_store_ops; >>=20 >> static int jump__scnprintf(struct ins *ins, char *bf, size_t size, >> struct ins_operands *ops, int max_ins_name);