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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Long Zhao <longzhao@ambarella.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	 Alexandre Belloni <alexandre.belloni@bootlin.com>,
	soc@lists.linux.dev,  linux-arm-kernel@lists.infradead.org,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@kernel.org>,
	Linus Walleij <linusw@kernel.org>,
	 Bartosz Golaszewski <brgl@kernel.org>,
	 Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	 Jiri Slaby <jirislaby@kernel.org>,
	 Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	 Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,  Long Zhao <zl020895@163.com>,
	Lee Jones <lee@kernel.org>,
	 mfd@lists.linux.dev, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org,  linux-gpio@vger.kernel.org,
	linux-serial <linux-serial@vger.kernel.org>,
	 LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 11/13] serial: 8250_dw: add Ambarella CV75 quirks
Date: Thu, 10 Sep 2026 11:44:35 +0300 (EEST)	[thread overview]
Message-ID: <07cdbec9-49af-d500-d93d-56bfcef9f490@linux.intel.com> (raw)
In-Reply-To: <20260904-cv75-v5-v6-11-e918514cb3b1@ambarella.com>

On Fri, 4 Sep 2026, Long Zhao via B4 Relay wrote:

> From: Long Zhao <longzhao@ambarella.com>
> 
> The Ambarella CV75 UART is Ambarella IP, not a Synopsys DesignWare
> licensed block. At the register level it is close enough to DW APB UART
> that a full custom UART driver is unnecessary: reuse 8250_dw with a
> small platform quirk.
> 
> Quirks:
> - keep IER ETOI (bit 5) set for RX timeout behaviour
> - skip set_rate; baud clock is managed outside the UART block
> 
> Signed-off-by: Long Zhao <longzhao@ambarella.com>
> ---
>  drivers/tty/serial/8250/8250_dw.c | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 5fba913f3301..b15de40d1e2a 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -43,6 +43,9 @@
>  #define RZN1_UART_xDMACR_8_WORD_BURST	(2 << 1)
>  #define RZN1_UART_xDMACR_BLK_SZ(x)	((x) << 3)
>  
> +/* Ambarella IER: receive timeout interrupt enable */
> +#define AMBARELLA_UART_IER_ETOI		BIT(5)
> +
>  /* Quirks */
>  #define DW_UART_QUIRK_OCTEON		BIT(0)
>  #define DW_UART_QUIRK_ARMADA_38X	BIT(1)
> @@ -60,6 +63,7 @@
>  
>  struct dw8250_platform_data {
>  	u8 usr_reg;
> +	u8 ier_mask;
>  	u32 cpr_value;
>  	unsigned int quirks;
>  };
> @@ -572,6 +576,27 @@ static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
>  	dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
>  }
>  
> +static int dw8250_ier_mask_startup(struct uart_port *p)
> +{
> +	struct dw8250_data *d = to_dw8250_data(p->private_data);
> +	struct uart_8250_port *up = up_to_u8250p(p);
> +	int ret;
> +
> +	ret = serial8250_do_startup(p);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Ambarella keeps variant IER bits (e.g. ETOI) set for correct RX
> +	 * timeout behaviour. Force them into the 8250 IER shadow so later
> +	 * generic IER updates do not clear them.
> +	 */
> +	up->ier |= d->pdata->ier_mask;
> +	serial_port_out(p, UART_IER, up->ier);

serial8250_do_startup() seems to defer IER update on purpose. Is it fine 
to override that behavior here?

-- 
 i.

> +	return 0;
> +}
> +
>  static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
>  {
>  	unsigned int quirks = data->pdata->quirks;
> @@ -606,6 +631,8 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
>  		p->serial_in = dw8250_serial_in32;
>  		data->uart_16550_compatible = true;
>  	}
> +	if (data->pdata->ier_mask)
> +		p->startup = dw8250_ier_mask_startup;
>  }
>  
>  static void dw8250_reset_control_assert(void *data)
> @@ -879,6 +906,12 @@ static const struct dw8250_platform_data dw8250_intc10ee = {
>  	.quirks = DW_UART_QUIRK_IER_KICK,
>  };
>  
> +static const struct dw8250_platform_data dw8250_ambarella_cv75_data = {
> +	.usr_reg = DW_UART_USR,
> +	.ier_mask = AMBARELLA_UART_IER_ETOI,
> +	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
> +};
> +
>  static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = {
>  	.usr_reg = DW_UART_USR,
>  	.cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) |
> @@ -889,6 +922,7 @@ static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = {
>  };
>  
>  static const struct of_device_id dw8250_of_match[] = {
> +	{ .compatible = "ambarella,cv75-uart", .data = &dw8250_ambarella_cv75_data },
>  	{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
>  	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
>  	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
> 
> 

  parent reply	other threads:[~2026-09-10  8:44 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-04  6:38 [PATCH v6 00/13] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-09-04  6:38 ` [PATCH v6 01/13] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-09-04 22:39   ` Linus Walleij
2026-09-04  6:38 ` [PATCH v6 02/13] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Long Zhao via B4 Relay
2026-09-08  9:52   ` Krzysztof Kozlowski
2026-09-04  6:38 ` [PATCH v6 03/13] dt-bindings: clock: add Ambarella CV75 RCT Long Zhao via B4 Relay
2026-09-08  9:52   ` Krzysztof Kozlowski
2026-09-04  6:38 ` [PATCH v6 04/13] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Long Zhao via B4 Relay
2026-09-04 22:40   ` Linus Walleij
2026-09-04  6:38 ` [PATCH v6 05/13] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-09-04 14:45   ` Rob Herring
2026-09-04  6:38 ` [PATCH v6 06/13] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart Long Zhao via B4 Relay
2026-09-04 22:41   ` Linus Walleij
2026-09-09  7:12   ` Krzysztof Kozlowski
2026-09-04  6:38 ` [PATCH v6 07/13] clk: ambarella: add CV75 CCU driver Long Zhao via B4 Relay
2026-09-04  7:44   ` Jerome Brunet
2026-09-04  9:21     ` zl020895
2026-09-04  6:38 ` [PATCH v6 08/13] gpio: regmap: support write_data_after_dir and girq Long Zhao via B4 Relay
2026-09-04 11:55   ` Andy Shevchenko
2026-09-07  4:20     ` zl020895
2026-09-07  4:45       ` Andy Shevchenko
2026-09-07 10:29         ` zl020895
2026-09-10  9:30           ` Andy Shevchenko
2026-09-04  6:38 ` [PATCH v6 09/13] gpio: pl061: use gpio-regmap and add Ambarella layout Long Zhao via B4 Relay
2026-09-04 13:14   ` Andy Shevchenko
2026-09-04  6:38 ` [PATCH v6 10/13] pinctrl: ambarella: add CV75 pin controller Long Zhao via B4 Relay
2026-09-04 13:29   ` Andy Shevchenko
2026-09-04  6:38 ` [PATCH v6 11/13] serial: 8250_dw: add Ambarella CV75 quirks Long Zhao via B4 Relay
2026-09-04 22:43   ` Linus Walleij
2026-09-10  8:33   ` Andy Shevchenko
2026-09-10  9:12     ` zl020895
2026-09-10  9:27       ` Andy Shevchenko
2026-09-10  9:33         ` Ilpo Järvinen
2026-09-10  9:45           ` zl020895
2026-09-10 15:39             ` Andy Shevchenko
2026-09-10  8:44   ` Ilpo Järvinen [this message]
2026-09-10  9:15     ` zl020895
2026-09-04  6:38 ` [PATCH v6 12/13] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-09-04 22:45   ` Linus Walleij
2026-09-04  6:38 ` [PATCH v6 13/13] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
2026-09-04 22:45   ` Linus Walleij
2026-09-04  6:54 ` [PATCH v6 00/13] Ambarella CV75 SoC minimal bring-up Jerome Brunet
2026-09-04  6:56   ` Krzysztof Kozlowski
2026-09-11 12:55     ` Jerome Brunet
2026-09-11 12:57       ` Krzysztof Kozlowski

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