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Wed, 9 Jul 2025 08:53:50 +0000 (GMT) From: "Pritam Manohar Sutar" To: "'Krzysztof Kozlowski'" Cc: , , , , , , , , , , , , , , , , , , , , , , In-Reply-To: <20250706-diamond-crab-of-will-72205e@krzk-bin> Subject: RE: [PATCH v4 5/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo SS phy Date: Wed, 9 Jul 2025 14:23:49 +0530 Message-ID: <07d501dbf0ae$ff2126a0$fd6373e0$@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQJAgQZ9LFXBZrDskwNBYris6jFv1AJ630FZAevjVggA58dhDrM15xjg Content-Language: en-in X-CMS-MailID: 20250709085353epcas5p3e1e989544692330277c3096f40df8369 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250701120009epcas5p46bc2870446c499f9c0008c1d396650bb References: <20250701120706.2219355-1-pritam.sutar@samsung.com> <20250701120706.2219355-6-pritam.sutar@samsung.com> <20250706-diamond-crab-of-will-72205e@krzk-bin> Hi Krzysztof, > -----Original Message----- > From: Krzysztof Kozlowski > Sent: 06 July 2025 03:14 PM > To: Pritam Manohar Sutar > Cc: vkoul=40kernel.org; kishon=40kernel.org; robh=40kernel.org; > krzk+dt=40kernel.org; conor+dt=40kernel.org; alim.akhtar=40samsung.com; > andre.draszik=40linaro.org; peter.griffin=40linaro.org; neil.armstrong=40= linaro.org; > kauschluss=40disroot.org; ivo.ivanov.ivanov1=40gmail.com; > m.szyprowski=40samsung.com; s.nawrocki=40samsung.com; linux- > phy=40lists.infradead.org; devicetree=40vger.kernel.org; linux- > kernel=40vger.kernel.org; linux-arm-kernel=40lists.infradead.org; linux-s= amsung- > soc=40vger.kernel.org; rosa.pila=40samsung.com; dev.tailor=40samsung.com; > faraz.ata=40samsung.com; muhammed.ali=40samsung.com; > selvarasu.g=40samsung.com > Subject: Re: =5BPATCH v4 5/6=5D dt-bindings: phy: samsung,usb3-drd-phy: a= dd > ExynosAutov920 combo SS phy >=20 > On Tue, Jul 01, 2025 at 05:37:05PM +0530, Pritam Manohar Sutar wrote: > > This phy supports USB3.1 SSP+(10Gbps) protocol and is backwards >=20 > Agian, this? >=20 > > compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is required to > > support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates. > > These two phys are combined to form a combo phy. > > > > Add a dedicated compatible string for USB combo SS phy found in this > > SoC. The SoC requires two clocks, named =22phy=22 and =22ref=22 and var= ious > > power supplies (regulators) for the internal circuitry to work. > > The required voltages are: > > * avdd075_usb - 0.75v > > * avdd18_usb20 - 1.8v > > * avdd33_usb20 - 3.3v >=20 > One more commitm message completely copy-pasted and completely > uninforming. The voltages are irrelevant. Explain the architecture. This = should be > just one patch with proper full description. >=20 > > > > Add schema only for 'USB3.1 SSP+' SS phy in this commit. >=20 > Why only? Add everything, describe everything, but not what voltages you = have > there but the architecture of the PHY. >=20 Will combine patch 3 (combo HS phy) & 5(combo SS phy) to describe combo phy= and even will add some details as mentioned in cover letter. > Best regards, > Krzysztof