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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-67070815d27sm2964601a12.24.2026.04.14.04.54.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Apr 2026 04:54:02 -0700 (PDT) Message-ID: <07ff689e-39dc-4f3d-b68f-3f3942916283@oss.qualcomm.com> Date: Tue, 14 Apr 2026 13:53:57 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions To: jsandom@axon.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260409-rb5gen2-dts-v3-0-be736355d4b4@axon.com> <20260409-rb5gen2-dts-v3-1-be736355d4b4@axon.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260409-rb5gen2-dts-v3-1-be736355d4b4@axon.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE0MDExMCBTYWx0ZWRfX9asseHU0BmW+ LQ7DN0xQAWSSyGeSsljP35MVlZrVQ1pOb/66YW1S+UIsrwqmtH4uT4sLW/E+dS7y54sOFhP/Vl8 3nmPqv9NFMSd9hOL7626Wv14oKmDstgltMoT1J/dlK0h1hqRaAWSETtKZBTX0dclYvLOtREKPfl dHLYkigTO8H4+ZbHopi5/rlux3YfNR+Ce4uik6SnIVxmC1DUYkEReobhNQ5FPIxyCVftTn8xtnB AtgiKP5j79V3Vv22weNwhqEVof68MHNJ5mnk5A+eo08VcOBczLagWM1tEC3GOx5U4k4BTEoP/OO 2Z9Fl4SlsPl48ek9qu25Qu9p6Hs6RJ9jH37QhfqTDx1v6/qGCXZ9svW9OCN7aVIYpnmjP1Ovf4z NER0JFqQJ1+t8xNqVpiAQSXAePCTNjRWpaDxV/e0in4gC0YZpy9Z/sPk4bgsZWXj5luAu/CzJfw LKwOl6Ricasgj4sg7eQ== X-Proofpoint-ORIG-GUID: 5opd4rm_SfotfO2044cdke1HyGMnBvIr X-Proofpoint-GUID: 5opd4rm_SfotfO2044cdke1HyGMnBvIr X-Authority-Analysis: v=2.4 cv=btZ8wkai c=1 sm=1 tr=0 ts=69de2add cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=h77gEMGJAAAA:8 a=EUspDBNiAAAA:8 a=mYbSqgcRFfY83x1HOF0A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=PYyYjrCoJcZo81GydsRF:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-14_03,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604140110 On 4/9/26 5:26 PM, Joe Sandom via B4 Relay wrote: > From: Joe Sandom > > Add the MHI register regions to the pcie0 and pcie1 controller nodes > to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2) > via debugfs. The PCIe host driver uses this region to read the > link_transition_count from the MHI registers. > > Signed-off-by: Joe Sandom > --- Reviewed-by: Konrad Dybcio Konrad