From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADBE925BEF8 for ; Sat, 24 Jan 2026 23:21:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769296892; cv=none; b=u+Zx0VyGy91HlY+zte+SqvJZP5LYKeEmLNdaE2kaBVR7u3gj2/K38apX3ZNgkMnwegcD+LRkxraXnQKodKTL+1/SEy51YTKMnstTT9uXH6BlP0JghZjfeDZh49lqkOsNrVCX4266ObpQSAJCHFDCNhdN+iQ1QEeYElJ3DsE76qE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769296892; c=relaxed/simple; bh=Se+XgkrMv5HfloTeudL4/5zk4ovq+p9aIUYDgD9jhW0=; h=Date:From:To:cc:Subject:Message-ID:MIME-Version:Content-Type; b=eIJefwYxcZNL6vJmVfF2BWgwsNZKhO+3pMv/WzaFs76beu8yPMBnYlFJM0vxWSX2M7HR1cKDPDZc41Sk101kM3vla8cxfT2ThIe/RNHSrnmFYQYuf1DBBUoclAvtXGGyk4wEztb2XBWJ2elA7cBvkas8iYr1vYOeEdUSDSeL25A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d3mDGNK7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d3mDGNK7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 033FFC19421; Sat, 24 Jan 2026 23:21:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769296892; bh=Se+XgkrMv5HfloTeudL4/5zk4ovq+p9aIUYDgD9jhW0=; h=Date:From:To:cc:Subject:From; b=d3mDGNK703aa4KOM9Pz7rjI11v05b/dhklAjUWMYTbrrUoazzS5JH67KEmXN4FK3m CpspSzMfksgziMabD0AYvN21u7TKqYH3i+X9GaPfxsgLS9RD6gEos0Kw6A0lFQNw3d +LUQUzAG5BQEue12h0VYgkTnqRQvQBmT+FxqCXMHKZ/muXVNLPuLLx+1YxUewcgmrf WncreHql2GyC3oRt9814bAZKlbk60J2W+0abNkBxn0wUQLlyhxVwM5agFuQSUNUYTP 4tT3m6vQ76xe0SI4950cD1kO1u8imXwQWdNzwtgJgEwoPwlnypiAgtH3anSnZtR0og 1YKE9C+7UAZHw== Date: Sat, 24 Jan 2026 16:21:29 -0700 (MST) From: Paul Walmsley To: torvalds@linux-foundation.org cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V updates for v6.19-rc7 Message-ID: <081aefd5-d47d-8397-693a-3e0a3c73783e@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Linus, Please pull these RISC-V fixes for v6.19-rc7. The notable changes here are the three RISC-V timer compare register update sequence patches. These only apply to RV32 systems and are related to the 64-bit timer compare value being split across two separate 32-bit registers. We weren't using the appropriate three-write sequence, documented in the RISC-V ISA specifications, to avoid spurious timer interrupts during the update sequence; so, these patches now use the recommended sequence. This doesn't affect 64-bit RISC-V systems, since the timer compare value fits inside a single register and can be updated with a single write. thanks, - Paul The following changes since commit 0f61b1860cc3f52aef9036d7235ed1f017632193: Linux 6.19-rc5 (2026-01-11 17:03:14 -1000) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux tags/riscv-for-linus-6.19-rc7 for you to fetch changes up to 841e47d56cef9b96fd2314220e3d0f1d92c719f4: riscv: Add intermediate cast to 'unsigned long' in __get_user_asm (2026-01-22 20:21:14 -0700) ---------------------------------------------------------------- RISC-V updates for v6.19-rc7 - Fix the RISC-V timer compare register update sequence on RV32 systems to use the recommended sequence in the RISC-V ISA manual. This avoids spurious interrupts during updates - Add a dependence on the new CONFIG_CACHEMAINT_FOR_DMA Kconfig symbol for Renesas and StarFive RISC-V SoCs - Add a temporary workaround for a Clang compiler bug caused by using asm_goto_output for get_user() - Clarify our documentation around to specifically state a particular ISA specification version for a chapter number reference ---------------------------------------------------------------- Guodong Xu (1): Documentation: riscv: uabi: Clarify ISA spec version for canonical order Jonathan Cameron (2): riscv: ERRATA_STARFIVE_JH7100: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA soc: renesas: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA Naohiko Shimizu (3): riscv: clocksource: Fix stimecmp update hazard on RV32 riscv: kvm: Fix vstimecmp update hazard on RV32 riscv: suspend: Fix stimecmp update hazard on RV32 Nathan Chancellor (2): riscv: Use 64-bit variable for output in __get_user_asm riscv: Add intermediate cast to 'unsigned long' in __get_user_asm Documentation/arch/riscv/uabi.rst | 4 +++- arch/riscv/Kconfig.errata | 1 + arch/riscv/include/asm/uaccess.h | 14 ++++++++++++-- arch/riscv/kernel/suspend.c | 3 ++- arch/riscv/kvm/vcpu_timer.c | 6 ++++-- drivers/clocksource/timer-riscv.c | 3 ++- drivers/soc/renesas/Kconfig | 1 + 7 files changed, 25 insertions(+), 7 deletions(-)