From: Marc Zyngier <marc.zyngier@arm.com>
To: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>,
bhelgaas@google.com, paul.gortmaker@windriver.com,
robh@kernel.org, colin.king@canonical.com,
linux-pci@vger.kernel.org
Cc: michal.simek@xilinx.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, rgummal@xilinx.com, arnd@arndb.de,
Bharat Kumar Gogada <bharatku@xilinx.com>
Subject: Re: [PATCH v2 2/2] PCI: Xilinx NWL: Fix, proc interrupts for legacy virtual irq shown as edge
Date: Wed, 25 Jan 2017 09:24:14 +0000 [thread overview]
Message-ID: <0833bdec-b05e-57c0-c740-ac7735036450@arm.com> (raw)
In-Reply-To: <1485334353-26815-2-git-send-email-bharatku@xilinx.com>
On 25/01/17 08:52, Bharat Kumar Gogada wrote:
> - Legacy interrupts are level triggered, virtual irq line of End
> Point shows as edge in /proc/interrupts.
> - Setting irq flags of virtual irq line of EP to level triggered
> at the time of mapping.
>
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> ---
> drivers/pci/host/pcie-xilinx-nwl.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
> index 6ac3e1d..1cddd1f 100644
> --- a/drivers/pci/host/pcie-xilinx-nwl.c
> +++ b/drivers/pci/host/pcie-xilinx-nwl.c
> @@ -434,6 +434,7 @@ static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
> {
> irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
> irq_set_chip_data(irq, domain->host_data);
> + irq_set_status_flags(irq, IRQ_LEVEL);
>
> return 0;
> }
>
As said in my previous review [1], this should be folded in the previous
patch, as it doesn't make much sense on its own.
Thanks,
M.
[1] http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1316912.html
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2017-01-25 9:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-25 8:52 [PATCH v2 1/2] PCI: Xilinx NWL: Modifying irq chip for legacy interrupts Bharat Kumar Gogada
2017-01-25 8:52 ` [PATCH v2 2/2] PCI: Xilinx NWL: Fix, proc interrupts for legacy virtual irq shown as edge Bharat Kumar Gogada
2017-01-25 9:24 ` Marc Zyngier [this message]
2017-01-30 5:57 ` Bharat Kumar Gogada
2017-01-25 9:23 ` [PATCH v2 1/2] PCI: Xilinx NWL: Modifying irq chip for legacy interrupts Marc Zyngier
2017-01-30 5:56 ` Bharat Kumar Gogada
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