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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb58b303bsm9592715ad.38.2026.05.22.00.52.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 May 2026 00:52:04 -0700 (PDT) Message-ID: <083fc602-7549-4abe-a11e-51dae9fd0c8f@oss.qualcomm.com> Date: Fri, 22 May 2026 15:51:57 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 15/39] drm/msm/dp: Add support for programming p1/p2/p3 register blocks To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> <20260410-msm-dp-mst-v4-15-b20518dea8de@oss.qualcomm.com> <55081f4d-f1a9-42c7-a1cd-cdcefc008668@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: FBOlzBHaIwg48qm5ihQsqcReMLooDPDP X-Authority-Analysis: v=2.4 cv=QblWeMbv c=1 sm=1 tr=0 ts=6a100b26 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=6TMII061o9s9I29nBW0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: FBOlzBHaIwg48qm5ihQsqcReMLooDPDP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIyMDA3NyBTYWx0ZWRfXyG3YEgwSdMo+ /rcwlNzhNWsNXsVrO2TiAts7s5wuI96dL8FmAM3D/YGwrkO41YwDn47AiVm0Vhmf0/VHeJUClZD KL76Ns8HF6MAshSqJewKvK1LNCjDKGgd2fziR9o5qOccdGMwNHPHRfXz+QfoemALPn6jvMQy3wh +3PMn5M+YizpmlG0xdBTA6KU8M5dy+K6rPZ/FVjS0a9AFDUT1yiNUz2EpL6SM+r3/IVe84FYYQv 5qHqTlpeoFyUxIe2tX4DukU0EcEbDfHEW2sIxqyICKo7pd+781HVfZWnhL1j50jr2pf8NO7LhjQ IqlvAklVtuToKHIw85510qmVTeZ4wZzZm6yHelFNILE+GozSKRnXF73E2OjMWICaournDR9JqzF D3w4TJGR5oKQrg53/8HqgBlmJrPQ7ArXheCy6I6AtrMqYOdrWF0KbNpvwfVmTV6mKLvTA3hpiQs 0+etBdZrNY26ZpWJ9aQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-22_01,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 adultscore=0 clxscore=1015 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220077 On 5/21/2026 8:20 PM, Dmitry Baryshkov wrote: > On Thu, May 21, 2026 at 07:50:30PM +0800, Yongxing Mou wrote: >> >> >> On 4/12/2026 2:07 AM, Dmitry Baryshkov wrote: >>> On Fri, Apr 10, 2026 at 05:33:50PM +0800, Yongxing Mou wrote: >>>> From: Abhinav Kumar >>>> >>>> Add support for additional pixel register blocks (p1, p2, p3) to enable >>>> 4‑stream MST pixel clocks. Introduce the helper functions msm_dp_read_pn >>>> and msm_dp_write_pn for pixel register programming. All pixel clocks >>>> share the same register layout but use different base addresses. >>>> >>>> Signed-off-by: Abhinav Kumar >>>> Signed-off-by: Yongxing Mou >>>> --- >>>> drivers/gpu/drm/msm/dp/dp_display.c | 40 ++++++++++++----- >>>> drivers/gpu/drm/msm/dp/dp_panel.c | 89 ++++++++++++++++++++----------------- >>>> drivers/gpu/drm/msm/dp/dp_panel.h | 3 +- >>>> 3 files changed, 79 insertions(+), 53 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c >>>> index 7984a0f9e938..ff506064a3fa 100644 >>>> --- a/drivers/gpu/drm/msm/dp/dp_display.c >>>> +++ b/drivers/gpu/drm/msm/dp/dp_display.c >>>> @@ -85,8 +85,8 @@ struct msm_dp_display_private { >>>> void __iomem *link_base; >>>> size_t link_len; >>>> - void __iomem *p0_base; >>>> - size_t p0_len; >>>> + void __iomem *pixel_base[DP_STREAM_MAX]; >>>> + size_t pixel_len; >>>> int max_stream; >>>> }; >>>> @@ -561,7 +561,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) >>>> goto error_link; >>>> } >>>> - dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->p0_base); >>>> + dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->pixel_base[0]); >>>> if (IS_ERR(dp->panel)) { >>>> rc = PTR_ERR(dp->panel); >>>> DRM_ERROR("failed to initialize panel, rc = %d\n", rc); >>>> @@ -769,6 +769,7 @@ int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, >>>> } >>>> panel->stream_id = stream_id; >>>> + msm_dp_panel_set_pixel_base(panel, dp->pixel_base[stream_id]); >>> >>> Hmmm.... Would it be better to set it up differently? Allocate one panel >>> per the stream from the beginning and then simply get the first >>> available panel when required? This would require some minimal resource >>> manager, but then we won't have to pass dummy register base to the panel >>> code. Or actually allocate a panel when it is required? Do we need a >>> panel before atomic_enable()? >>> >> In this series, panel come with MST connectors, Because the connectors are >> dynamically assigned, we don’t know which connector corresponds to which >> stream, so there stream_id and pixel base address are dynamic. > > I read this as 'streams are dynamically assigned'. Connectors are fixed > and created for each branch point / real physical connector. Streams are > assigned on the first-serve bases. > Thanks for pointing that out — your statement here is accurate. >> we have 2 optionals here: > > What is the runtime requirement for the panels? Are they required for > parsing of the resources or only for the setup of the actual screen? > > If we have 5 monitors connected to a single DP controller (via the > complicated topology), how many msm_dp_panel instances do we need to > handle the case, present it to the user and still let it select only 4 > of them for the video output? > It seems that if we move the link-related resources from the panel into dp_link, struct msm_dp_panel { /* dpcd raw data */ u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; struct msm_dp_link_info link_info; ... } we would only need to assign the panel during atomic_enable / atomic_disable. This way, in the scenario you described, only the final four panels would be exposed to the user. In the current implementation, the panel contains link-related information that is required during the link training phase. >> 1.panel come with encoder (after bridge remvoed), like that: >> struct msm_dp_mst_encoder { >> struct drm_encoder *enc; >> int stream_id; >> struct msm_dp_panel *dp_panel; >> }; > > This sounds like a good idea. This way there is no additional resource > management, etc. > >> 2. During enable and disable, allocate and release dynamically. >> would you prefer which one? >>>> return rc; >>>> } >