From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45FC9EB64D9 for ; Thu, 15 Jun 2023 07:06:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244460AbjFOHGq (ORCPT ); Thu, 15 Jun 2023 03:06:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243703AbjFOHGS (ORCPT ); Thu, 15 Jun 2023 03:06:18 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 936C62728; Thu, 15 Jun 2023 00:06:08 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35F4Emsg006244; Thu, 15 Jun 2023 07:06:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=XWWiSC/2cMr8EAAI65Nfl+3f3bXFbZqlZsIW7m/HUGc=; b=WTvWiVr1JrjJpOIa7ecIVp6SWZ90cJifn02F4HX/8VGlfmaIXkegSBA0nu/Eh0j5qrJV CKZZ9LqCGusTBDDN3FwPuonwMYaDB8240O/FnHxAueF/ZRKeHQbWbcwYq2VXBpoaBsZg OeSO40Rrie7MHXA1H/decsSerX4KQU6S9cXrmqLeMVDXqGhECFCHMNaNvGOdQt54u08y o9b2THMhALz2TuLIH8a9YNQJyss+jkdfG3XIm/7UCRCAmMY+L+igzXOIUtGjNJeAMM54 8ni2dVWK1vuAIAvrjWH2WBRp0f8K5SFR0EpeL0DEdm3W2C01+s/eLiYZt8QKW6M9fwx9 Vw== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r7u8c8aru-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jun 2023 07:06:05 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35F764q9024838 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jun 2023 07:06:04 GMT Received: from [10.110.8.184] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 15 Jun 2023 00:06:00 -0700 Message-ID: <0848ee33-edd6-6f2c-a8d2-b374a1e0a378@quicinc.com> Date: Thu, 15 Jun 2023 12:35:56 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH 2/2] spi: spi-geni-qcom: Add SPI SLAVE mode support for GENI based QuPv3 Content-Language: en-US To: Shazad Hussain , , , , , , , CC: , , , References: <20230613065229.5619-1-quic_ptalari@quicinc.com> <20230613065229.5619-3-quic_ptalari@quicinc.com> <886b1665-cbb9-e302-eb2d-b7ff9fd242a8@quicinc.com> From: Praveen Talari In-Reply-To: <886b1665-cbb9-e302-eb2d-b7ff9fd242a8@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: s5WarNst3qgWcdAl0Hm_Cf8wLRXTMT6x X-Proofpoint-GUID: s5WarNst3qgWcdAl0Hm_Cf8wLRXTMT6x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-15_04,2023-06-14_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306150058 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Thank you for review. On 6/13/2023 1:12 PM, Shazad Hussain wrote: > > > On 6/13/2023 12:22 PM, Praveen Talari wrote: >> Add SPI SLAVE mode support for GENI based QuPv3. >> >> Signed-off-by: Praveen Talari >> --- >>   drivers/spi/spi-geni-qcom.c | 55 +++++++++++++++++++++++++++++++++---- >>   1 file changed, 49 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c >> index 206cc04bb1ed..2e3ae29e79e0 100644 >> --- a/drivers/spi/spi-geni-qcom.c >> +++ b/drivers/spi/spi-geni-qcom.c >> @@ -12,6 +12,7 @@ >>   #include >>   #include >>   #include >> +#include >>   #include >>   #include >>   #include >> @@ -52,6 +53,9 @@ >>   #define SPI_CS_CLK_DELAY_MSK        GENMASK(19, 10) >>   #define SPI_CS_CLK_DELAY_SHFT        10 >>   +#define SE_SPI_SLAVE_EN                (0x2BC) >> +#define SPI_SLAVE_EN                BIT(0) >> + >>   /* M_CMD OP codes for SPI */ >>   #define SPI_TX_ONLY        1 >>   #define SPI_RX_ONLY        2 >> @@ -99,6 +103,24 @@ struct spi_geni_master { >>       int cur_xfer_mode; >>   }; >>   +static struct spi_master *get_spi_master(struct device *dev) >> +{ >> +    struct platform_device *pdev = to_platform_device(dev); >> +    struct spi_master *spi = platform_get_drvdata(pdev); >> + >> +    return spi; >> +} >> + >> +static void spi_slv_setup(struct spi_geni_master *mas) >> +{ >> +    struct geni_se *se = &mas->se; >> + >> +    writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN); >> +    writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL); >> +    writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); >> +    dev_info(mas->dev, "spi slave setup done\n"); >> +} >> + >>   static int get_spi_clk_cfg(unsigned int speed_hz, >>               struct spi_geni_master *mas, >>               unsigned int *clk_idx, >> @@ -140,12 +162,18 @@ static void handle_se_timeout(struct spi_master >> *spi, >>       const struct spi_transfer *xfer; >>         spin_lock_irq(&mas->lock); >> -    reinit_completion(&mas->cancel_done); >>       if (mas->cur_xfer_mode == GENI_SE_FIFO) >>           writel(0, se->base + SE_GENI_TX_WATERMARK_REG); >>         xfer = mas->cur_xfer; >>       mas->cur_xfer = NULL; >> + >> +    if (spi->slave) { >> +        spin_unlock_irq(&mas->lock); >> +        goto unmap_if_dma; >> +    } >> + >> +    reinit_completion(&mas->cancel_done); >>       geni_se_cancel_m_cmd(se); >>       spin_unlock_irq(&mas->lock); >>   @@ -541,6 +569,8 @@ static bool geni_can_dma(struct spi_controller >> *ctlr, >>         if (mas->cur_xfer_mode == GENI_GPI_DMA) >>           return true; >> +    if (ctlr->slave) >> +        return true; >>         len = get_xfer_len_in_words(xfer, mas); >>       fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / >> mas->cur_bits_per_word; >> @@ -619,6 +649,7 @@ static void spi_geni_release_dma_chan(struct >> spi_geni_master *mas) >>     static int spi_geni_init(struct spi_geni_master *mas) >>   { >> +    struct spi_master *spi = get_spi_master(mas->dev); >>       struct geni_se *se = &mas->se; >>       unsigned int proto, major, minor, ver; >>       u32 spi_tx_cfg, fifo_disable; >> @@ -627,7 +658,14 @@ static int spi_geni_init(struct spi_geni_master >> *mas) >>       pm_runtime_get_sync(mas->dev); >>         proto = geni_se_read_proto(se); >> -    if (proto != GENI_SE_SPI) { >> + >> +    if (spi->slave) { >> +        if (proto != GENI_SE_SPI_SLAVE) { >> +            dev_err(mas->dev, "Invalid proto %d\n", proto); >> +            goto out_pm; >> +        } >> +        spi_slv_setup(mas); >> +    } else if (proto != GENI_SE_SPI) { >>           dev_err(mas->dev, "Invalid proto %d\n", proto); >>           goto out_pm; >>       } >> @@ -677,9 +715,11 @@ static int spi_geni_init(struct spi_geni_master >> *mas) >>       } >>         /* We always control CS manually */ >> -    spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); >> -    spi_tx_cfg &= ~CS_TOGGLE; >> -    writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); >> +    if (!spi->slave) { >> +        spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); >> +        spi_tx_cfg &= ~CS_TOGGLE; >> +        writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); >> +    } >>     out_pm: >>       pm_runtime_put(mas->dev); >> @@ -1072,6 +1112,9 @@ static int spi_geni_probe(struct >> platform_device *pdev) >>       pm_runtime_set_autosuspend_delay(&pdev->dev, 250); >>       pm_runtime_enable(dev); >>   +    if (device_property_read_bool(&pdev->dev, "qcom,slv-ctrl")) > > Should we update this property "qcom,slv-ctrl" in device tree bindings > as well !! Done > > >> +        spi->slave = true; >> + >>       ret = geni_icc_get(&mas->se, NULL); >>       if (ret) >>           goto spi_geni_probe_runtime_disable; >> @@ -1092,7 +1135,7 @@ static int spi_geni_probe(struct >> platform_device *pdev) >>        * for dma (gsi) mode, the gsi will set cs based on params >> passed in >>        * TRE >>        */ >> -    if (mas->cur_xfer_mode == GENI_SE_FIFO) >> +    if (!spi->slave && mas->cur_xfer_mode == GENI_SE_FIFO) >>           spi->set_cs = spi_geni_set_cs; >>         ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), >> spi); > > -Shazad