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Thu, 15 Aug 2024 08:59:39 -0700 (PDT) Received: from [100.64.0.1] ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-824e990d5b4sm57205339f.14.2024.08.15.08.59.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Aug 2024 08:59:38 -0700 (PDT) Message-ID: <085c8332-d7f1-41df-8854-bee06291ba83@sifive.com> Date: Thu, 15 Aug 2024 10:59:37 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 0/9] Fix Allwinner D1 boot regression To: Emil Renner Berthing , Anup Patel , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> <87jzgjnh9z.ffs@tglx> <87ttfmm2ns.ffs@tglx> <87plqalyd4.ffs@tglx> <686d61c4-e7ac-4dca-a7fd-decdd72e84d9@sifive.com> <87h6blnaf1.ffs@tglx> Content-Language: en-US From: Samuel Holland In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Emil, On 2024-08-15 10:07 AM, Emil Renner Berthing wrote: > Samuel Holland wrote: >> On 2024-08-15 9:16 AM, Anup Patel wrote: >>> On Thu, Aug 15, 2024 at 7:41 PM Thomas Gleixner wrote: >>>> >>>> On Thu, Aug 15 2024 at 08:32, Samuel Holland wrote: >>>>> On 2024-08-15 8:16 AM, Thomas Gleixner wrote: >>>>>> Yes. So the riscv timer is not working on this thing or it stops >>>>>> somehow. >>>>> >>>>> That's correct. With the (firmware) devicetree that Emil is using, the OpenSBI >>>>> firmware does not have a timer device, so it does not expose the (optional[1]) >>>>> SBI time extension, and sbi_set_timer() does nothing. >>>> >>>> Sigh. Does RISCV really have to repeat all mistakes which have been made >>>> by x86, ARM and others before? It's known for decades that the kernel >>>> relies on a working timer... >>> >>> My apologies for the delay in finding a fix for this issue. >>> >>> Almost all RISC-V platforms (except this one) have SBI Timer always >>> available and Linux uses a better timer or Sstc extension whenever >>> it is available. >> >> So this is the immediate solution: add the CLINT to the firmware devicetree so >> that the SBI time extension works, and Linux will boot without any code changes, >> albeit with a higher-overhead clockevent device. > > But this will mean that you can't update your kernel to v6.9 or newer without > reflashing OpenSBI and u-boot. That's still a regression right? I suppose that depends on if you think the SBI time extension is (or should have been) mandatory for platforms without Sstc. If the SBI time extension is mandatory, then this is a firmware bug, and not really Linux's responsibility to work around. If the SBI time extension is not mandatory, then Linux needs to be able to handle platforms where the S-mode visible timer is attached to an external interrupt controller (PLIC or APLIC), so the irqchip driver needs to be loaded before time_init() (timer_probe()). So in that case, the bug is a Linux regression, and we would need to revert the platform driver conversion. Regards, Samuel