From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: "mturquette@baylibre.com" <mturquette@baylibre.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"krzysztof.kozlowski+dt@linaro.org"
<krzysztof.kozlowski+dt@linaro.org>
Cc: "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"angelogioacchino.delregno@collabora.com"
<angelogioacchino.delregno@collabora.com>,
"nfraprado@collabora.com" <nfraprado@collabora.com>,
"Chun-Jie Chen (陳浚桀)" <Chun-Jie.Chen@mediatek.com>,
"wenst@chromium.org" <wenst@chromium.org>,
"Runyang Chen (陈润洋)" <Runyang.Chen@mediatek.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [PATCH v8 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195
Date: Mon, 20 Jun 2022 14:40:46 +0800 [thread overview]
Message-ID: <08653b784294bb11182faf82c74757a14d780c4e.camel@mediatek.com> (raw)
In-Reply-To: <20220523060056.24396-17-rex-bc.chen@mediatek.com>
On Mon, 2022-05-23 at 14:00 +0800, Rex-BC Chen wrote:
> We will use mediatek clock reset as infracfg_ao reset instead of
> ti-syscon. To support this, remove property of ti reset and add
> property of #reset-cells for mediatek clock reset.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 ++-------------
> 1 file changed, 2 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index b57e620c2c72..db16eba9d475 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -10,7 +10,6 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> -#include <dt-bindings/reset/ti-syscon.h>
>
> / {
> compatible = "mediatek,mt8195";
> @@ -292,20 +291,10 @@
> };
>
> infracfg_ao: syscon@10001000 {
> - compatible = "mediatek,mt8195-infracfg_ao",
> "syscon", "simple-mfd";
> + compatible = "mediatek,mt8195-infracfg_ao",
> "syscon";
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> -
> - infracfg_rst: reset-controller {
> - compatible = "ti,syscon-reset";
> - #reset-cells = <1>;
> - ti,reset-bits = <
> - 0x140 18 0x144 18 0 0
> (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
> - 0x120 0 0x124 0 0 0
> (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> - 0x730 10 0x734 10 0 0
> (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> - 0x150 5 0x154 5 0 0
> (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
> - >;
> - };
> + #reset-cells = <1>;
> };
>
> pericfg: syscon@10003000 {
> --
> 2.18.0
>
Hello Matthias,
driver part is accepted by Setphen[1].
dts part is also reviewed.
Is these dts parts ok for you? (including patch 15 and 16)
Or should I send another series for dts part?
Thanks!
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/log/?h=clk-next
BRs,
Bo-Chen
next prev parent reply other threads:[~2022-06-20 6:41 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-23 6:00 [PATCH v8 00/19] Cleanup MediaTek clk reset drivers and support SoCs Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 01/19] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 02/19] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 03/19] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 04/19] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 05/19] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 06/19] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 07/19] clk: mediatek: reset: Support nonsequence base offsets of reset registers Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 08/19] clk: mediatek: reset: Support inuput argument index mode Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 09/19] clk: mediatek: reset: Change return type for clock reset register function Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 10/19] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 11/19] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 12/19] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 13/19] dt-bindings: reset: mediatek: Add infra_ao reset index " Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 14/19] clk: mediatek: reset: Add infra_ao reset support " Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 15/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Rex-BC Chen
2022-06-20 6:40 ` Rex-BC Chen [this message]
2022-05-23 6:00 ` [PATCH v8 17/19] dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 Rex-BC Chen
2022-05-23 9:05 ` AngeloGioacchino Del Regno
2022-05-23 9:16 ` Rex-BC Chen
2022-05-23 6:00 ` [PATCH v8 18/19] dt-bindings: arm: mediatek: Add #reset-cells property " Rex-BC Chen
2022-05-23 9:09 ` AngeloGioacchino Del Regno
2022-05-23 6:00 ` [PATCH v8 19/19] clk: mediatek: reset: Add infra_ao reset support " Rex-BC Chen
2022-05-23 9:17 ` AngeloGioacchino Del Regno
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