From: Sylwester Nawrocki <s.nawrocki@samsung.com>
To: Lukasz Luba <l.luba@partner.samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org,
kyungmin.park@samsung.com, m.szyprowski@samsung.com,
myungjoo.ham@samsung.com,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC
Date: Fri, 01 Feb 2019 15:19:30 +0100 [thread overview]
Message-ID: <08850f80-0cc1-8e0d-6a8a-286a750d3a8c@samsung.com> (raw)
In-Reply-To: <0ca15b4c-ddaa-1be5-35be-e76b008b28a8@partner.samsung.com>
On 2/1/19 14:56, Lukasz Luba wrote:
>> Exynos5422 used the same PLL table for apll, kpll, bpll and so on.
>> You don't need to make the separate pll table. Just add new entries
>> to exynos5420_pll2550x_24mhz_tbl table.
> OK, I will extend the exynos5420_pll2550x_24mhz_tbl table.
>
> In v4 patch set, it will be fixed.
I would prefer to keep the rate table separate for BPLL, until correctness
of new rates introduced in the patch and their applicability to the other PLLs
is confirmed by the hardware team and verified in tests.
--
Regards,
Sylwester
next prev parent reply other threads:[~2019-02-01 14:19 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190131085005eucas1p1b218446d0112714bd784e54dd0167155@eucas1p1.samsung.com>
2019-01-31 8:49 ` [PATCH v3 0/8] Exynos5 Dynamic Memory Controller driver Lukasz Luba
[not found] ` <CGME20190131085006eucas1p2e4ba3f69e039c394e7cd42389ac8bfa7@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Lukasz Luba
2019-02-01 7:40 ` Chanwoo Choi
2019-02-01 13:49 ` Lukasz Luba
[not found] ` <CGME20190131085006eucas1p1ca478545c107086d427909c88d3b232e@eucas1p1.samsung.com>
2019-01-31 8:49 ` [PATCH v3 2/8] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
2019-02-01 8:07 ` Chanwoo Choi
2019-02-01 9:20 ` Chanwoo Choi
2019-02-01 13:03 ` Lukasz Luba
[not found] ` <CGME20190131085007eucas1p2f16107042b8ce5638811840618bcf017@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
2019-02-01 8:44 ` Chanwoo Choi
2019-02-01 13:56 ` Lukasz Luba
2019-02-01 14:19 ` Sylwester Nawrocki [this message]
2019-02-01 15:39 ` Lukasz Luba
2019-02-03 7:54 ` Chanwoo Choi
2019-02-11 10:21 ` Lukasz Luba
2019-02-11 10:34 ` Chanwoo Choi
[not found] ` <CGME20190131085008eucas1p237fe9e2f8cb6254e8da7c97c2984e6b2@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 4/8] drivers: devfreq: add DMC driver for Exynos5422 Lukasz Luba
[not found] ` <CGME20190131085009eucas1p14c96bc345bc4c414e6c4d7506f14e69c@eucas1p1.samsung.com>
2019-01-31 8:49 ` [PATCH v3 5/8] dt-bindings: devfreq: add Exynos5422 DMC device description Lukasz Luba
[not found] ` <CGME20190131085009eucas1p166467551006e54130905ebb5eefdefab@eucas1p1.samsung.com>
2019-01-31 8:49 ` [PATCH v3 6/8] DT: arm: exynos: add DMC device for exynos5422 Lukasz Luba
[not found] ` <CGME20190131085010eucas1p2b2bdc90be27dfd73f13d41ed0d725bb2@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 7/8] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
[not found] ` <CGME20190131085011eucas1p2c315d69c8902fbceff689f3a92e0c5d9@eucas1p2.samsung.com>
2019-01-31 8:49 ` [PATCH v3 8/8] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
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