From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3] arm64: dts: qcom: glymur: add coresight nodes
Date: Mon, 18 May 2026 10:09:02 +0800 [thread overview]
Message-ID: <08fc1b02-50a4-4ba3-9588-24d0a9d7d039@oss.qualcomm.com> (raw)
In-Reply-To: <20260515-add-coresight-nodes-for-glymur-v3-1-83ab39db275d@oss.qualcomm.com>
On 5/15/2026 4:11 PM, Jie Gan wrote:
> Add CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF.
> These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and
> some small subsystems, such as GCC, IPCC, PMU and so on.
>
> Delete cti_wpss DT node on Mahua since this device will cause NoC issue
> on Mahua device.
>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
[...]
> +
> + tn@11200000 {
> + compatible = "qcom,coresight-tnoc", "arm,primecell";
> + reg = <0x0 0x11200000 0x0 0x4200>;
Made a mistake here, the MMIO size should be 0x3c00 for the traceNoC
device on Glymur platform. Will send a new version to fix it.
Sorry for the mistake.
Thanks,
Jie
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@6 {
> + reg = <6>;
> +
> + tn_ag_in6: endpoint {
> + remote-endpoint = <&mm_dsb_tpdm_out>;
> + };
> + };
> +
> + port@10 {
> + reg = <0x10>;
> +
> + tn_ag_in16: endpoint {
> + remote-endpoint = <&east_dsb_tpdm_out>;
> + };
> + };
> +
> + port@21 {
> + reg = <0x21>;
> +
> + tn_ag_in33: endpoint {
> + remote-endpoint = <&west_dsb_tpdm_out>;
> + };
> + };
> +
> + port@23 {
> + reg = <0x23>;
> +
> + tn_ag_in35: endpoint {
> + remote-endpoint = <&qm_tpdm_out>;
> + };
> + };
> +
> + port@24 {
> + reg = <0x24>;
> +
> + tn_ag_in36: endpoint {
> + remote-endpoint = <&gcc_tpdm_out>;
> + };
> + };
> +
> + port@32 {
> + reg = <0x32>;
> +
> + tn_ag_in50: endpoint {
> + remote-endpoint = <&pcie_rscc_tpda_out>;
> + };
> + };
> +
> + port@35 {
> + reg = <0x35>;
> +
> + tn_ag_in53: endpoint {
> + remote-endpoint = <&cdsp_funnel_out>;
> + };
> + };
> +
> + port@3f {
> + reg = <0x3f>;
> +
> + tn_ag_in63: endpoint {
> + remote-endpoint = <¢er_dsb_tpdm_out>;
> + };
> + };
> +
> + port@40 {
> + reg = <0x40>;
> +
> + tn_ag_in64: endpoint {
> + remote-endpoint = <&ipcc_cmb_tpdm_out>;
> + };
> + };
> +
> + port@41 {
> + reg = <0x41>;
> +
> + tn_ag_in65: endpoint {
> + remote-endpoint = <&qrng_tpdm_out>;
> + };
> + };
> +
> + port@42 {
> + reg = <0x42>;
> +
> + tn_ag_in66: endpoint {
> + remote-endpoint = <&pmu_tpdm_out>;
> + };
> + };
> +
> + port@43 {
> + reg = <0x43>;
> +
> + tn_ag_in67: endpoint {
> + remote-endpoint = <&rdpm_west_cmb0_tpdm_out>;
> + };
> + };
> +
> + port@44 {
> + reg = <0x44>;
> +
> + tn_ag_in68: endpoint {
> + remote-endpoint = <&rdpm_west_cmb1_tpdm_out>;
> + };
> + };
> +
> + port@45 {
> + reg = <0x45>;
> +
> + tn_ag_in69: endpoint {
> + remote-endpoint = <&rdpm_west_cmb2_tpdm_out>;
> + };
> + };
> +
> + port@4b {
> + reg = <0x4b>;
> +
> + tn_ag_in75: endpoint {
> + remote-endpoint = <&south_dsb2_tpdm_out>;
> + };
> + };
> +
> + port@52 {
> + reg = <0x52>;
> +
> + tn_ag_in82: endpoint {
> + remote-endpoint = <&south_dsb_tpdm_out>;
> + };
> + };
> +
> + port@53 {
> + reg = <0x53>;
> +
> + tn_ag_in83: endpoint {
> + remote-endpoint = <¢er_dsb1_tpdm_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + tn_ag_out: endpoint {
> + remote-endpoint = <&funnel0_in0>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11207000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11207000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,dsb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + mm_dsb_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in6>;
> + };
> + };
> + };
> + };
> +
> + tpdm@1120b000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x1120b000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,dsb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + east_dsb_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in16>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11213000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11213000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,dsb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + west_dsb_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in33>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11219000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11219000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,dsb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + center_dsb_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in63>;
> + };
> + };
> + };
> + };
> +
> + tpdm@1121a000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x1121a000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + ipcc_cmb_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in64>;
> + };
> + };
> + };
> + };
> +
> + tpdm@1121b000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x1121b000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + qrng_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in65>;
> + };
> + };
> + };
> + };
> +
> + tpdm@1121c000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x1121c000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,dsb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + pmu_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in66>;
> + };
> + };
> + };
> + };
> +
> + tpdm@1121d000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x1121d000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + rdpm_west_cmb0_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in67>;
> + };
> + };
> + };
> + };
> +
> + tpdm@1121e000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x1121e000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + rdpm_west_cmb1_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in68>;
> + };
> + };
> + };
> + };
> +
> + tpdm@1121f000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x1121f000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + rdpm_west_cmb2_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in69>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11220000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11220000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,dsb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + center_dsb1_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in83>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11224000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11224000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,dsb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + south_dsb2_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in75>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11228000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11228000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,dsb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + south_dsb_tpdm_out: endpoint {
> + remote-endpoint = <&tn_ag_in82>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11470000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11470000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-element-bits = <32>;
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + pcie_rscc_tpdm_out: endpoint {
> + remote-endpoint = <&pcie_rscc_tpda_in0>;
> + };
> + };
> + };
> + };
> +
> + tpda@11471000 {
> + compatible = "qcom,coresight-tpda", "arm,primecell";
> + reg = <0x0 0x11471000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + pcie_rscc_tpda_in0: endpoint {
> + remote-endpoint = <&pcie_rscc_tpdm_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + pcie_rscc_tpda_out: endpoint {
> + remote-endpoint = <&tn_ag_in50>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11c03000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11c03000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-element-bits = <64>;
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + swao_prio4_tpdm_out: endpoint {
> + remote-endpoint = <&aoss_tpda_in4>;
> + };
> + };
> + };
> + };
> +
> + funnel@11c04000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x0 0x11c04000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@5 {
> + reg = <5>;
> +
> + aoss_funnel_in5: endpoint {
> + remote-endpoint = <&aoss_tpda_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> +
> + aoss_funnel_in6: endpoint {
> + remote-endpoint = <&funnel0_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + aoss_funnel_out: endpoint {
> + remote-endpoint = <&etf0_in>;
> + };
> + };
> + };
> + };
> +
> + tmc_etf: tmc@11c05000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x11c05000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + etf0_in: endpoint {
> + remote-endpoint = <&aoss_funnel_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + etf0_out: endpoint {
> + remote-endpoint = <&swao_rep_in>;
> + };
> + };
> + };
> + };
> +
> + replicator@11c06000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x0 0x11c06000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + swao_rep_in: endpoint {
> + remote-endpoint = <&etf0_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + swao_rep_out1: endpoint {
> + remote-endpoint = <&eud_in>;
> + };
> + };
> + };
> + };
> +
> + tpda@11c08000 {
> + compatible = "qcom,coresight-tpda", "arm,primecell";
> + reg = <0x0 0x11c08000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + aoss_tpda_in0: endpoint {
> + remote-endpoint = <&swao_prio0_tpdm_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + aoss_tpda_in1: endpoint {
> + remote-endpoint = <&swao_prio1_tpdm_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + aoss_tpda_in2: endpoint {
> + remote-endpoint = <&swao_prio2_tpdm_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> +
> + aoss_tpda_in3: endpoint {
> + remote-endpoint = <&swao_prio3_tpdm_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> +
> + aoss_tpda_in4: endpoint {
> + remote-endpoint = <&swao_prio4_tpdm_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> +
> + aoss_tpda_in5: endpoint {
> + remote-endpoint = <&swao_tpdm_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + aoss_tpda_out: endpoint {
> + remote-endpoint = <&aoss_funnel_in5>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11c09000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11c09000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-element-bits = <64>;
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + swao_prio0_tpdm_out: endpoint {
> + remote-endpoint = <&aoss_tpda_in0>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11c0a000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11c0a000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-element-bits = <64>;
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + swao_prio1_tpdm_out: endpoint {
> + remote-endpoint = <&aoss_tpda_in1>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11c0b000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11c0b000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-element-bits = <64>;
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + swao_prio2_tpdm_out: endpoint {
> + remote-endpoint = <&aoss_tpda_in2>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11c0c000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11c0c000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,cmb-element-bits = <64>;
> + qcom,cmb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + swao_prio3_tpdm_out: endpoint {
> + remote-endpoint = <&aoss_tpda_in3>;
> + };
> + };
> + };
> + };
> +
> + tpdm@11c0d000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x0 0x11c0d000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,dsb-element-bits = <32>;
> + qcom,dsb-msrs-num = <32>;
> +
> + out-ports {
> + port {
> + swao_tpdm_out: endpoint {
> + remote-endpoint = <&aoss_tpda_in5>;
> + };
> + };
> + };
> + };
> +
> apps_smmu: iommu@15000000 {
> compatible = "qcom,glymur-smmu-500",
> "qcom,smmu-500",
> @@ -7132,4 +8173,60 @@ gpuss-1-critical {
> };
> };
> };
> +
> + tpdm-cdsp-llm {
> + compatible = "qcom,coresight-static-tpdm";
> + qcom,cmb-element-bits = <32>;
> +
> + out-ports {
> + port {
> + cdsp_llm_tpdm_out: endpoint {
> + remote-endpoint = <&cdsp_tpda_in1>;
> + };
> + };
> + };
> + };
> +
> + tpdm-cdsp-llm2 {
> + compatible = "qcom,coresight-static-tpdm";
> + qcom,cmb-element-bits = <32>;
> +
> + out-ports {
> + port {
> + cdsp_llm2_tpdm_out: endpoint {
> + remote-endpoint = <&cdsp_tpda_in2>;
> + };
> + };
> + };
> + };
> +
> + tpdm-cdsp-cmsr {
> + compatible = "qcom,coresight-static-tpdm";
> +
> + qcom,cmb-element-bits = <32>;
> + qcom,dsb-element-bits = <32>;
> +
> + out-ports {
> + port {
> + cdsp_cmsr_tpdm_out: endpoint {
> + remote-endpoint = <&cdsp_tpda_in3>;
> + };
> + };
> + };
> + };
> +
> + tpdm-cdsp-cmsr2 {
> + compatible = "qcom,coresight-static-tpdm";
> +
> + qcom,cmb-element-bits = <32>;
> + qcom,dsb-element-bits = <32>;
> +
> + out-ports {
> + port {
> + cdsp_cmsr2_tpdm_out: endpoint {
> + remote-endpoint = <&cdsp_tpda_in4>;
> + };
> + };
> + };
> + };
> };
> diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi
> index 990a02c6afc1..22822b6b2e8b 100644
> --- a/arch/arm64/boot/dts/qcom/mahua.dtsi
> +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi
> @@ -21,6 +21,7 @@
> /delete-node/ &cpu_pd15;
> /delete-node/ &cpu_pd16;
> /delete-node/ &cpu_pd17;
> +/delete-node/ &cti_wpss;
> /delete-node/ &thermal_aoss_6;
> /delete-node/ &thermal_aoss_7;
> /delete-node/ &thermal_cpu_2_0_0;
>
> ---
> base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
> change-id: 20260515-add-coresight-nodes-for-glymur-49045aa9ede8
>
> Best regards,
prev parent reply other threads:[~2026-05-18 2:09 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-15 8:11 Jie Gan
2026-05-18 2:09 ` Jie Gan [this message]
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