From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2882744C50B; Wed, 14 Oct 2026 06:41:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791960083; cv=none; b=DMG58RAP8U7ahO+j81P1+9A5yknRo7RzAwpuEajd9OFnRMt0hCz9uOp74DtLbkCRR2MqokCWvOeg8POiNnqS1KWdqq4pzBP+ceB8cSM4kntw01fbvexB+IhdEFjzhP1wGBc/3Oy3DlKQaMyDpn36QCZZubhVlsouyydFoj5PBQE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791960083; c=relaxed/simple; bh=7TZib+f/as+GdEvahZGxF0OZFyn7Mkkh4KJyPfJCo2U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S7wzKaKvBoyX5yC/zr0lszO7Uo0/z5wMzJkZLKyswE1461zjTAgErkdIr2nds9iH16sab1OGL139mgL4WaV+SKoAOyZJkKLbW+lhsuwetvc5ltDU4vxnLRrr0bPUb3VRs7a4SqQgBgKgdgSJeTwdrxYnRDppyYxcxrASUTUHFUA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=FtdOHZrS; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="FtdOHZrS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1791960082; x=1823496082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7TZib+f/as+GdEvahZGxF0OZFyn7Mkkh4KJyPfJCo2U=; b=FtdOHZrSE9plUfMpPCy9W1vy9OU7/1IpZA+zd5XPWQcJm9PTIfkbxj3R /6IeI86QYAg1AoBq7fb/E4rBHR52SEaokdawZYT4PQK9LAWD9PH2/uTTd 5VOWu/DS9Pv8e/0vZXlDlY9y8U5USjmnGvz4L7WKT01uBAjMhpnKjyMg5 qtTuBQnKPYntbvnnfHt3EnVDWqwzacbiEYGUM2uKDvh3KBy/XyOlm6iqA kOkmBL9ldhm8Pd5RZcFNwuoXngl3FPjrgIn+ln7Nxz+Ar8SCURK6f8uYC vgyp/Sm23IOKZfmmwtnoz1sPnu59gvkvUbBF0ctJTLJNx6VH7s214XTqv w==; X-CSE-ConnectionGUID: fElzlNT3SvWZ+sjmV6A6zw== X-CSE-MsgGUID: 0KPszsrXR4WyufAHBKQc4Q== X-IronPort-AV: E=Sophos;i="6.27,157,1787036400"; d="scan'208";a="65288678" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2026 23:41:21 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Tue, 13 Oct 2026 23:41:20 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 13 Oct 2026 23:41:12 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v8 4/8] mtd: spi-nor: sfdp: expose the SFDP as a read-only NVMEM device Date: Wed, 14 Oct 2026 12:10:08 +0530 Message-ID: <093672d183a06dc2f37366b2f9ff144316850863.1790847519.git.manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain The SPI NOR core already reads the SFDP tables during enumeration and caches them in nor->sfdp->dwords (see spi_nor_parse_sfdp()). Re-expose that cached data as a read-only NVMEM device, in on-flash byte order, rooted at the flash's SFDP child node (compatible "jedec,sfdp"). This lets NVMEM cells reference any SFDP data: a fixed-layout for parameters at a known offset, or an nvmem-layout parser for vendor data whose location must be discovered at runtime. The device is only registered when an "sfdp" node is present in the device tree. Signed-off-by: Manikandan Muralidharan --- drivers/mtd/spi-nor/core.c | 78 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 8bc117b46e02..4e47459b1679 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -3001,6 +3002,75 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; } +static int spi_nor_sfdp_reg_read(void *priv, unsigned int offset, + void *val, size_t bytes) +{ + struct spi_nor *nor = priv; + struct sfdp *sfdp = nor->sfdp; + size_t sfdp_size = sfdp->num_dwords * sizeof(*sfdp->dwords); + + if (offset >= sfdp_size || bytes > sfdp_size - offset) + return -EINVAL; + + /* The cached SFDP is kept in on-flash (little-endian) byte order. */ + memcpy(val, (u8 *)sfdp->dwords + offset, bytes); + + return 0; +} + +/** + * spi_nor_register_sfdp_nvmem() - expose the SFDP as a read-only NVMEM device + * @nor: pointer to a 'struct spi_nor' + * + * Expose the whole SFDP, in on-flash byte order, as a read-only NVMEM device + * rooted at the flash's SFDP child node (compatible "jedec,sfdp"). This lets + * generic (fixed-layout) or vendor (nvmem-layout) cells reference any SFDP + * data. The device is only registered when a child node with the "jedec,sfdp" + * compatible is described in the device tree. + * + * Return: 0 on success or if there is nothing to do, -errno otherwise. + */ +static int spi_nor_register_sfdp_nvmem(struct spi_nor *nor) +{ + struct device *dev = nor->dev; + struct nvmem_config config = { }; + struct nvmem_device *nvmem; + struct device_node *np; + + if (!nor->sfdp) + return 0; + + np = of_get_compatible_child(dev_of_node(dev), "jedec,sfdp"); + if (!np) + return 0; + + config.dev = dev; + config.of_node = np; + config.name = "sfdp"; + config.id = NVMEM_DEVID_AUTO; + config.owner = THIS_MODULE; + config.read_only = true; + config.word_size = 1; + config.stride = 1; + config.size = (int)(nor->sfdp->num_dwords * sizeof(*nor->sfdp->dwords)); + config.reg_read = spi_nor_sfdp_reg_read; + config.priv = nor; + + nvmem = devm_nvmem_register(dev, &config); + of_node_put(np); + if (IS_ERR(nvmem)) { + /* NVMEM support is optional. */ + if (PTR_ERR(nvmem) == -EOPNOTSUPP) + return 0; + return dev_err_probe(dev, PTR_ERR(nvmem), + "failed to register SFDP NVMEM device\n"); + } + + dev_dbg(dev, "exposed %d-byte SFDP as an NVMEM device\n", config.size); + + return 0; +} + /** * spi_nor_late_init_params() - Late initialization of default flash parameters. * @nor: pointer to a 'struct spi_nor' @@ -3204,6 +3274,14 @@ static int spi_nor_init_params(struct spi_nor *nor) spi_nor_init_params_deprecated(nor); } + /* + * Expose the SFDP table as an NVMEM device only when + * the flash actually provides one + */ + ret = spi_nor_register_sfdp_nvmem(nor); + if (ret) + return ret; + ret = spi_nor_late_init_params(nor); if (ret) return ret; -- 2.43.0