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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa5996de7f2sm276477266b.53.2024.11.30.04.51.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 30 Nov 2024 04:51:48 -0800 (PST) Message-ID: <095ad153-db49-4e95-98ac-f896f1826e21@oss.qualcomm.com> Date: Sat, 30 Nov 2024 13:51:46 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V6 4/4] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider To: Krzysztof Kozlowski , Raviteja Laggyshetty , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Odelu Kukatla , Mike Tipton , Sibi Sankar , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241125174511.45-1-quic_rlaggysh@quicinc.com> <20241125174511.45-5-quic_rlaggysh@quicinc.com> <67c9a6d8-90ea-41f4-baac-1d67c9e5576e@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <67c9a6d8-90ea-41f4-baac-1d67c9e5576e@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: GK_dsPT84jErmCQUzHNt3_ALARVgG4AF X-Proofpoint-ORIG-GUID: GK_dsPT84jErmCQUzHNt3_ALARVgG4AF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 clxscore=1015 bulkscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2411300106 On 27.11.2024 8:21 PM, Krzysztof Kozlowski wrote: > On 25/11/2024 18:45, Raviteja Laggyshetty wrote: >> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P >> SoCs. >> Update the generic compatible for SM8250 and SC7280 SoCs to >> "qcom,epss-l3-perf" as they use PERF_STATE register for L3 scaling. >> >> Signed-off-by: Raviteja Laggyshetty >> --- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++ >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- >> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- >> 3 files changed, 21 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> index 9f315a51a7c1..0c2bd15f9ef0 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> @@ -10,6 +10,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -4282,6 +4283,15 @@ rpmhpd_opp_turbo_l1: opp-9 { >> }; >> }; >> >> + epss_l3_cl0: interconnect@18590000 { >> + compatible = "qcom,sm8250-epss-l3", >> + "qcom,epss-l3-perf"; > This is sa8775p, not sm8250. Wrong compatible. The bigger issue here is that a treewide binding adjustment is coupled with a feature addition in a single patch. They should be separate. Konrad