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Mon, 13 Jan 2025 03:32:02 -0800 (PST) Received: from [10.81.35.177] ([46.149.103.10]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c9646c51sm494684266b.172.2025.01.13.03.32.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Jan 2025 03:32:01 -0800 (PST) Message-ID: <09807556-46fe-46ae-ae3f-7083a1b12253@citrix.com> Date: Mon, 13 Jan 2025 11:32:00 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird To: riel@surriel.com Cc: akpm@linux-foundation.org, bp@alien8.de, dave.hansen@linux.intel.com, jannh@google.com, kernel-team@meta.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, nadav.amit@gmail.com, peterz@infradead.org, thomas.lendacky@amd.com, x86@kernel.org, zhengqi.arch@bytedance.com References: <20250112155453.1104139-12-riel@surriel.com> Subject: Re: [PATCH v4 11/12] x86/mm: enable AMD translation cache extensions Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; 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charset=UTF-8 Content-Transfer-Encoding: 8bit > diff > > --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index > bcf73775b4f8..b7e84d43a22d 100644 --- a/arch/x86/kernel/cpu/amd.c +++ > b/arch/x86/kernel/cpu/amd.c @@ -1071,6 +1071,9 @@ static void > init_amd(struct cpuinfo_x86 *c) > /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ > clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); > + + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) + > msr_set_bit(MSR_EFER, _EFER_TCE); } > > #ifdef CONFIG_X86_32 I don't think this is wise.  TCE is orthogonal to INVLPGB. Either Linux is safe with TCE turned on, and it should be turned on everywhere (it goes back to Fam10h CPUs IIRC), or Linux isn't safe with TCE turned on, and this needs to depend on some other condition. Or, is this a typo and did you mean to check the TCE CPUID bit, rather than the INVLPGB CPUID bit? ~Andrew