From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3A16CD68E3 for ; Tue, 10 Oct 2023 02:27:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1441871AbjJJC1x (ORCPT ); Mon, 9 Oct 2023 22:27:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379403AbjJJC1v (ORCPT ); Mon, 9 Oct 2023 22:27:51 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 62E31A4 for ; Mon, 9 Oct 2023 19:27:50 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D172B1FB; Mon, 9 Oct 2023 19:28:30 -0700 (PDT) Received: from [10.163.61.202] (unknown [10.163.61.202]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BEF673F7A6; Mon, 9 Oct 2023 19:27:47 -0700 (PDT) Message-ID: <09877594-7d03-4f30-aec8-a0573bf295b8@arm.com> Date: Tue, 10 Oct 2023 07:57:45 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] driver: perf: arm_pmuv3: Read PMMIR_EL1 unconditionally To: James Clark , linux-arm-kernel@lists.infradead.org, zhangshaokun@hisilicon.com Cc: Will Deacon , Mark Rutland , linux-kernel@vger.kernel.org References: <20231009075631.193208-1-anshuman.khandual@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi James, On 10/9/23 14:29, James Clark wrote: > > > On 09/10/2023 08:56, Anshuman Khandual wrote: >> PMMIR_EL1 needs to be captured in 'armpmu->reg_pmmir', for all appropriate >> PMU version implementations where the register is available and reading it >> is valid . Hence checking for bus slot event presence is redundant and can >> be dropped. >> >> Cc: Will Deacon >> Cc: Mark Rutland >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Anshuman Khandual >> --- >> This applies on v6.6-rc5. >> >> drivers/perf/arm_pmuv3.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c >> index 1e72b486c033..9fc1b6da5106 100644 >> --- a/drivers/perf/arm_pmuv3.c >> +++ b/drivers/perf/arm_pmuv3.c >> @@ -1129,7 +1129,7 @@ static void __armv8pmu_probe_pmu(void *info) >> pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); >> >> /* store PMMIR register for sysfs */ >> - if (is_pmuv3p4(pmuver) && (pmceid_raw[1] & BIT(31))) >> + if (is_pmuv3p4(pmuver)) >> cpu_pmu->reg_pmmir = read_pmmir(); >> else >> cpu_pmu->reg_pmmir = 0; > > > This does have the side effect of showing non-zero values in caps/slots > even when the STALL_SLOT event isn't implemented. I think that's the > scenario that the original commit (f5be3a61fd) was trying to avoid: But the the sysfs interface is supposed to show all the PMMIR_EL1 based HW attributes as captured irrespective of bus slots event's presence as the register could be read on ARMv8.4-PMU without additional conditions imposed upon from the architecture. > > /sys/bus/event_source/devices/armv8_pmuv3_0/caps/slots is exposed > under sysfs. [If] Both ARMv8.4-PMU and STALL_SLOT event are > implemented, it returns the slots from PMMIR_EL1, otherwise it will > return 0. But that additional requirement of STALL_SLOT event is just SW mandated without any architectural backing. > > I can't really think of a scenario where that would be an issue, and the > availability of the STALL_SLOT event is already discoverable from > userspace through the events folder, so it's probably fine. Absolutely. > > Adding the original author just in case. But otherwise: > > Reviewed-by: James Clark Thanks !