From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753162AbdBUNL4 (ORCPT ); Tue, 21 Feb 2017 08:11:56 -0500 Received: from smtpout.microchip.com ([198.175.253.82]:33491 "EHLO email.microchip.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752623AbdBUNL0 (ORCPT ); Tue, 21 Feb 2017 08:11:26 -0500 Subject: Re: [PATCH v2 2/3] mtd: nand: atmel: Document the new DT bindings To: Boris Brezillon , Richard Weinberger , , Alexandre Belloni , Haavard Skinnemoen , Hans-Christian Egtvedt , , Wenyou Yang , Josh Wu References: <1487593718-20752-1-git-send-email-boris.brezillon@free-electrons.com> <1487593718-20752-3-git-send-email-boris.brezillon@free-electrons.com> CC: David Woodhouse , Brian Norris , Marek Vasut , Cyrille Pitchen , , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , From: Nicolas Ferre Organization: atmel Message-ID: <09a60016-5256-2ef2-c786-278c47d8c559@atmel.com> Date: Tue, 21 Feb 2017 14:11:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <1487593718-20752-3-git-send-email-boris.brezillon@free-electrons.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: =?Windows-1252?Q?H4sIAAAAAAAAC+NgFjrFJsWRWlGSWpSXmKPExsXCxeXDoltksybC4P3/?= =?Windows-1252?Q?DX1MFh3XFjNZHHixkMXiyIW1zBb3vp9ntph/5ByrxcSVk5ktutc9Yrfo?= =?Windows-1252?Q?f7OQ1eLH12YWi3OvVjJabHp8jdXi8q45bBa7m5axWxzdc4/ZYun1i0wW?= =?Windows-1252?Q?E6avZbHoPH6S1WLyzjeMFq17j7Bb3P61gcVBxGPNvDWMHgt+bWXxuNzX?= =?Windows-1252?Q?y+TxZNNFRo+ds+6ye6xc/oXNY/MKLY9NqzqBjCX1HjfnFXpsfv2C2WPR?= =?Windows-1252?Q?qc/sHp83yQXwRrFm5iXlVySwZkzb/Z294JB6xbVTT1kaGH/JdTFycQgJ?= =?Windows-1252?Q?rGCU+LxgFWsXIyeHsICXxKLTe5lBEiICTcwSl99sYYWoms0osa71PzuI?= =?Windows-1252?Q?wyywgVni0tUGFpAWNgFdibMTnrB1MXJw8AsIS5yZGg8S5hWwkZgzYyrY?= =?Windows-1252?Q?VBYBVYmfm/YwgdiiAhES85+uYoKoEZQ4OfMJ2BhOgWCJ1t+vmEFsZgED?= =?Windows-1252?Q?iSOL5rBC2PISzVtng8WFBFQk+t73s4PYEgKBEo17P0PZThLP191kg7Dt?= =?Windows-1252?Q?JA5PvwgVd5DoWvCbGabm6eOLULa2xPZX+1ghbB2JbQf7WSBsW4k9MyYy?= =?Windows-1252?Q?QdjuEg8eLYeyfSVmPWyAqomSaFuymW0Co9QsJC/MQnL2LCRnL2BkXsUo?= =?Windows-1252?Q?7ezhpxscpusa4exhYK6Xm5xRoJubmJmnl5yfu4kRkqpydjCuWRxxiFGS?= =?Windows-1252?Q?g0lJlDfbck2EEF9SfkplRmJxRnxRaU5q8SFGGQ4OJQleHyugnGBRanpq?= =?Windows-1252?Q?RVpmDjBpwqSZODgPMUpw8CiJ8FaA1PAWFyTmFmemQ+RPMUpKifNuB0kI?= =?Windows-1252?Q?gCQySvPgei8xikoJ87aC5HgKUotyM0sg4rcYxTgeMnE8ZhJiycvPS5UC?= =?Windows-1252?Q?OpUBCAwYXzGKczAqCfM2gbVk5pXArXkFdAET0AU3PVaCXFCSiJCSamAU?= =?Windows-1252?Q?lHT20yt6HempGngqz+DmzkeV2517zCdPNd191ftQ6y672vUn9u9RmzLv?= =?Windows-1252?Q?zrGAXM0JvDscXaqZlOdNSDXrzzzavyF9ksA8kW2tRX7Z6jb9Ivc0ZdjM?= =?Windows-1252?Q?Sj/PfbF5zjNBB5ekkruLim4rF/xzWTL3rhdvUuRbj2vCSb9/5eTVZOzT?= =?Windows-1252?Q?iLb58X1ST6wSS3FGoqEWc1FxIgBsi3Ur3QMAAA=3D=3D?= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 20/02/2017 à 13:28, Boris Brezillon a écrit : > The old NAND bindings were not exactly describing the hardware topology > and were preventing definitions of several NAND chips under the same > NAND controller. > > New bindings address these limitations and should be preferred over the > old ones for new SoCs/boards. > Old bindings are still supported for backward compatibility but are > marked deprecated in the doc. > > Signed-off-by: Boris Brezillon I think I already added it but here is my: Reviewed-by: Nicolas Ferre > --- > .../devicetree/bindings/mtd/atmel-nand.txt | 107 ++++++++++++++++++++- > 1 file changed, 106 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt > index 3e7ee99d3949..f6bee57e453a 100644 > --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt > +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt > @@ -1,4 +1,109 @@ > -Atmel NAND flash > +Atmel NAND flash controller bindings > + > +The NAND flash controller node should be defined under the EBI bus (see > +Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt). > +One or several NAND devices can be defined under this NAND controller. > +The NAND controller might be connected to an ECC engine. > + > +* NAND controller bindings: > + > +Required properties: > +- compatible: should be one of the following > + "atmel,at91rm9200-nand-controller" > + "atmel,at91sam9260-nand-controller" > + "atmel,at91sam9261-nand-controller" > + "atmel,at91sam9g45-nand-controller" > + "atmel,sama5d3-nand-controller" > +- ranges: empty ranges property to forward EBI ranges definitions. > +- #address-cells: should be set to 2. > +- #size-cells: should be set to 1. > +- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3 > + controllers. > +- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3 > + controllers. > + > +Optional properties: > +- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds > + a PMECC engine. > + > +* NAND device/chip bindings: > + > +Required properties: > +- reg: describes the CS lines assigned to the NAND device. If the NAND device > + exposes multiple CS lines (multi-dies chips), your reg property will > + contain X tuples of 3 entries. > + 1st entry: the CS line this NAND chip is connected to > + 2nd entry: the base offset of the memory region assigned to this > + device (always 0) > + 3rd entry: the memory region size (always 0x800000) > + > +Optional properties: > +- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND. > +- cs-gpios: the GPIO(s) used to control the CS line. > +- det-gpios: the GPIO used to detect if a Smartmedia Card is present. > +- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful > + on sama5 SoCs. > + > +All generic properties described in > +Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND > +device node, and NAND partitions should be defined under the NAND node as > +described in Documentation/devicetree/bindings/mtd/partition.txt. > + > +* ECC engine (PMECC) bindings: > + > +Required properties: > +- compatible: should be one of the following > + "atmel,at91sam9g45-pmecc" > + "atmel,sama5d4-pmecc" > + "atmel,sama5d2-pmecc" > +- reg: should contain 2 register ranges. The first one is pointing to the PMECC > + block, and the second one to the PMECC_ERRLOC block. > + > +Example: > + > + pmecc: ecc-engine@ffffc070 { > + compatible = "atmel,at91sam9g45-pmecc"; > + reg = <0xffffc070 0x490>, > + <0xffffc500 0x100>; > + }; > + > + ebi: ebi@10000000 { > + compatible = "atmel,sama5d3-ebi"; > + #address-cells = <2>; > + #size-cells = <1>; > + atmel,smc = <&hsmc>; > + reg = <0x10000000 0x10000000 > + 0x40000000 0x30000000>; > + ranges = <0x0 0x0 0x10000000 0x10000000 > + 0x1 0x0 0x40000000 0x10000000 > + 0x2 0x0 0x50000000 0x10000000 > + 0x3 0x0 0x60000000 0x10000000>; > + clocks = <&mck>; > + > + nand_controller: nand-controller { > + compatible = "atmel,sama5d3-nand-controller"; > + atmel,nfc-sram = <&nfc_sram>; > + atmel,nfc-io = <&nfc_io>; > + ecc-engine = <&pmecc>; > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + nand@3 { > + reg = <0x3 0x0 0x800000>; > + atmel,rb = <0>; > + > + /* > + * Put generic NAND/MTD properties and > + * subnodes here. > + */ > + }; > + }; > + }; > + > +----------------------------------------------------------------------- > + > +Deprecated bindings (should not be used in new device trees): > > Required properties: > - compatible: The possible values are: > -- Nicolas Ferre