Re: [PATCH v3 02/15] perf/x86/amd: Add IBS OP_DATA2 DataSrc bit definitions

[Ravi Bangoria <ravi.bangoria@amd.com>]

>>>> +/* IBS_OP_DATA2 DataSrc */
>>>> +#define IBS_DATA_SRC_LOC_CACHE                  2
>>>> +#define IBS_DATA_SRC_DRAM                       3
>>>> +#define IBS_DATA_SRC_REM_CACHE                  4
>>>> +#define IBS_DATA_SRC_IO                                 7
>>>> +
>>>> +/* IBS_OP_DATA2 DataSrc Extension */
>>>> +#define IBS_DATA_SRC_EXT_LOC_CACHE              1
>>>> +#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE                 2
>>>> +#define IBS_DATA_SRC_EXT_DRAM                   3
>>>> +#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE          5
>>>
>>> Is 4 undefined intentionally?
>>
>> Yes, Here is the snippet from PPR (Processor Programming Reference) doc:
>>
>>   Values | Description
>>   ---------------------------------------------------------------------
>>   0h     | No valid status.
>>   1h     | Local L3 or other L1/L2 in CCX.
>>   2h     | Another CCX cache in the same NUMA node.
>>   3h     | DRAM.
>>   4h     | Reserved.
>>   5h     | Another CCX cache in a different NUMA node.
>>   6h     | DRAM address map with "long latency" bit set.
>>   7h     | MMIO/Config/PCI/APIC.
>>   8h     | Extension Memory (S-Link, GenZ, etc - identified by the CS
>>          | target and/or address map at DF's choice).
>>   9h-Bh  | Reserved.
>>   Ch     | Peer Agent Memory.
>>   Dh-1Fh | Reserved.
> 
> Thanks for sharing it.  It's a bit confusing since it was available before.

Right, these bit definitions have changed in Zen4.

> 
> Anyway, is the PPR for Zen4 publicly available now?

Sadly, no. But it's in progress.

Thanks,
Ravi