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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36956527f45sm8028741a91.0.2026.05.19.00.52.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 May 2026 00:52:41 -0700 (PDT) Message-ID: <09c14a80-d981-4584-b4bb-8fb2430d7a0a@oss.qualcomm.com> Date: Tue, 19 May 2026 15:52:35 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 08/39] drm/msm/dp: allow dp_ctrl stream APIs to use any panel passed to it To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> <20260410-msm-dp-mst-v4-8-b20518dea8de@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: J7WhhXiTiEHgM4-9WtsK-aVH2zxazPeu X-Authority-Analysis: v=2.4 cv=eeUNubEH c=1 sm=1 tr=0 ts=6a0c16cb cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=WzSTVGcSt2Wm9MDnWl0A:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA3NiBTYWx0ZWRfX1YGCVUByF3C7 qmaKmHm4UQwPNZ4ykz3Ea4bbwWJw4+OKPk1PlMB2wf8U3vEm+jD9OfgMMjRdae0X30FRC2OZMS5 ltOTX/ysiUmhXXMRMZhQ6S1RGe66XL/Ed1yBvuvZEhBlGTfUE15wP/UpSd8CCO/KGmkC4Xhg6vr DKYb3lH+NBskVjmhbDRBGjvb3/jXmcnGvpYMd2bWUCdXa63z4xGcaEmz7UhDCQtvWdVCKztivVm tcP8jQFAQpuuever1+HnHo2yDneiTwkp3A3oHRMJcMS9emXwMyxyE84A/nMzPTXipAgneWAmd95 k2440VkkjnDgal5HxLvy/dI4V7cTXMQOIfhCLmdSI+VfezRfWRDXEbQc9lHXy2K4T9jAvK6c9ch 2xAQsVFymZW+RKu7IUIVAmVFc4TB7aj7HBd5J4uuVH70C9yef1ve3JBF03e7j5ONmPPTZxYM3cS TmxPmtG+ntWzleftQPg== X-Proofpoint-ORIG-GUID: J7WhhXiTiEHgM4-9WtsK-aVH2zxazPeu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190076 On 4/12/2026 1:38 AM, Dmitry Baryshkov wrote: > On Fri, Apr 10, 2026 at 05:33:43PM +0800, Yongxing Mou wrote: >> From: Abhinav Kumar >> >> Currently, the dp_ctrl stream APIs operate on their own dp_panel >> which is stored inside the dp_ctrl's private struct. However with MST, >> the stored panel represents the fixed link and not the sinks which >> are hotplugged. Allow the stream related APIs to work on the panel >> which is passed to them rather than the stored one. For SST cases, >> this shall continue to use the stored dp_panel. > > Hmm. Why? Can't we get rid of it (in the followup patch)? > In MST, the stream panel is bound to the connector, but in SST the panel is still stored in msm_dp_display_private and msm_dp_ctrl_private, so dropping it does not seem necessary at this point. The purpose of these changes is to allow the functions to operate on the MST panel data passed in per stream. >> >> Signed-off-by: Abhinav Kumar >> Signed-off-by: Yongxing Mou >> --- >> drivers/gpu/drm/msm/dp/dp_ctrl.c | 21 +++++++++++---------- >> drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- >> drivers/gpu/drm/msm/dp/dp_display.c | 2 +- >> 3 files changed, 13 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> index cd58968d4e14..d0eed8c7df45 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c >> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> @@ -477,13 +477,14 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, >> msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); >> } >> >> -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl) >> +static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl, >> + struct msm_dp_panel *msm_dp_panel) >> { >> - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); >> + msm_dp_ctrl_config_ctrl_streams(ctrl, msm_dp_panel); >> >> - msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); >> + msm_dp_ctrl_config_misc1_misc0(ctrl, msm_dp_panel); >> >> - msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); >> + msm_dp_panel_timing_cfg(msm_dp_panel, ctrl->msm_dp_ctrl.wide_bus_en); >> } >> >> /* >> @@ -2523,7 +2524,7 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_li >> return ret; >> } >> >> -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) >> +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel) >> { >> int ret = 0; >> bool mainlink_ready = false; >> @@ -2536,10 +2537,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) >> >> ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); >> >> - pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock; >> + pixel_rate_orig = msm_dp_panel->msm_dp_mode.drm_mode.clock; >> pixel_rate = pixel_rate_orig; >> >> - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) >> + if (msm_dp_ctrl->wide_bus_en || msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) >> pixel_rate >>= 1; >> >> drm_dbg_dp(ctrl->drm_dev, "pixel_rate=%lu\n", pixel_rate); >> @@ -2571,14 +2572,14 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) >> msm_dp_setup_peripheral_flush(ctrl); >> msm_dp_ctrl_config_ctrl_link(ctrl); >> >> - msm_dp_ctrl_configure_source_params(ctrl); >> + msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); >> >> msm_dp_ctrl_config_msa(ctrl, >> ctrl->link->link_params.rate, >> pixel_rate_orig, >> - ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); >> + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420); >> >> - msm_dp_panel_clear_dsc_dto(ctrl->panel); >> + msm_dp_panel_clear_dsc_dto(msm_dp_panel); >> >> msm_dp_ctrl_setup_tr_unit(ctrl); >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h >> index 5d615f50d13b..32196e97cbe9 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h >> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h >> @@ -17,7 +17,7 @@ struct msm_dp_ctrl { >> struct phy; >> >> int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); >> -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); >> +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel); >> int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); >> void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); >> void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); >> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c >> index 58c46d5ab4d8..1bf1335712bc 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_display.c >> +++ b/drivers/gpu/drm/msm/dp/dp_display.c >> @@ -666,7 +666,7 @@ static int msm_dp_display_enable(struct msm_dp_display_private *dp) >> return 0; >> } >> >> - rc = msm_dp_ctrl_on_stream(dp->ctrl); >> + rc = msm_dp_ctrl_on_stream(dp->ctrl, dp->panel); >> if (!rc) >> msm_dp_display->power_on = true; >> >> >> -- >> 2.43.0 >> >