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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adec8982f4esm352351666b.176.2025.06.14.12.09.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Jun 2025 12:09:05 -0700 (PDT) Message-ID: <09c40216-c0a2-4698-83b6-b838c28eed84@oss.qualcomm.com> Date: Sat, 14 Jun 2025 21:09:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 05/10] clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Will Deacon , Catalin Marinas Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov References: <20250612-qcs615-mm-v9-clock-controllers-v9-0-b34dc78d6e1b@quicinc.com> <20250612-qcs615-mm-v9-clock-controllers-v9-5-b34dc78d6e1b@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250612-qcs615-mm-v9-clock-controllers-v9-5-b34dc78d6e1b@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjE0MDE2MCBTYWx0ZWRfX1He+VBKathkq 5xGwQL2uxaDkf8evN7cuclAkhS/joYPSfLHzJ6u8M6ite7TIav5MzIY3P4UaNpkxothqPm7V5z7 CTRaNGa1JA6GHdB5TDBmxP7ZWk+yt1ZtNG3fO3xts1mIbC9x4G8p54IDj5lhJwtadUx8Yxo40lL Tsu7Q1aITj0tpyNBy1Sy7SMgP6D9qAd+pRRQW3H4AGkOLuNRt43k5MhC6VMLMdMm0KmxqD2sTmJ 4FFGmxUBvND9b1KhFSQEhtV0JnfynYN28d82Yncxs5tMUeWkQukj8fsxyf/+vIhmCLItSFlcfWa O5xS408O95ueFo2LhNrdKZJQS3bGvRPkc6STwgAIyc5xyFOf2DzwXvyvNUEmYjhyXAShlXJ/2Ew cTkwXIB9DiBafIVbggluCOr1ztplqRihO/pmXs9v+lOopv6fAxfcXu0TMMV37BCtTnU04fca X-Proofpoint-GUID: eBUl7GltvWNQUjQnW9UubAe8o5uGoCn_ X-Authority-Analysis: v=2.4 cv=NtnRc9dJ c=1 sm=1 tr=0 ts=684dc8d3 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=fbCSmPG1eNaTwHpC0zAA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: eBUl7GltvWNQUjQnW9UubAe8o5uGoCn_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-14_07,2025-06-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 adultscore=0 clxscore=1015 malwarescore=0 impostorscore=0 phishscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506140160 On 6/12/25 11:55 AM, Taniya Das wrote: > Add support for the display clock controller for display clients to > be able to request for the clocks on QCS615 platform. > > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Taniya Das > --- > +static int disp_cc_qcs615_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + > + regmap = qcom_cc_map(pdev, &disp_cc_qcs615_desc); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); > + > + /* Keep some clocks always enabled */ > + qcom_branch_set_clk_en(regmap, 0x6054); /* DISP_CC_XO_CLK */ > + > + return qcom_cc_really_probe(&pdev->dev, &disp_cc_qcs615_desc, regmap); Similarly: Reviewed-by: Konrad Dybcio Konrad