From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9FF3ECDE20 for ; Wed, 11 Sep 2019 07:36:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CBC8B222BF for ; Wed, 11 Sep 2019 07:36:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727127AbfIKHgM (ORCPT ); Wed, 11 Sep 2019 03:36:12 -0400 Received: from mail-sh.amlogic.com ([58.32.228.43]:56151 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726702AbfIKHgL (ORCPT ); Wed, 11 Sep 2019 03:36:11 -0400 Received: from [10.18.29.226] (10.18.29.226) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1591.10; Wed, 11 Sep 2019 15:37:02 +0800 Subject: Re: [PATCH v2 4/4] arm64: dts: add support for A1 based Amlogic AD401 To: Martin Blumenstingl CC: Kevin Hilman , , Rob Herring , Carlo Caione , Neil Armstrong , Jerome Brunet , , , , Jian Hu , Hanjie Lin , Xingyu Chen , Victor Wan , Qiufang Dai , Tao Zeng References: <1567667251-33466-1-git-send-email-jianxin.pan@amlogic.com> <1567667251-33466-5-git-send-email-jianxin.pan@amlogic.com> From: Jianxin Pan Message-ID: <09d7f5cc-9063-28f4-b68f-79f21fca500b@amlogic.com> Date: Wed, 11 Sep 2019 15:37:02 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.29.226] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Martin, On 2019/9/10 1:24, Martin Blumenstingl wrote: > Hi Jianxin, > > On Mon, Sep 9, 2019 at 2:03 PM Jianxin Pan wrote: >> >> Hi Martin, >> >> On 2019/9/7 23:02, Martin Blumenstingl wrote: >>> Hi Jianxin, >>> >>> On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote: >>> [...] >>>>> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...) here >>>>> aren't there any busses defined in the A1 SoC implementation or are >>>>> were you planning to add them later? >>>> Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no AO/EE power domain. >>>> Most of the registers are on the apb_32b bus. aobus, cbus and periphs are not used in A1. >>> OK, thank you for the explanation >>> since you're going to re-send the patch anyways: can you please >>> include the apb_32b bus? >>> all other upstream Amlogic .dts are using the bus definitions, so that >>> will make A1 consistent with the other SoCs >> In A1 (and the later C1), BUS is not mentioned in the memmap and register spec. >> Registers are organized and grouped by functions, and we can not find information about buses from the SoC document. > do you know why the busses are not part of the documentation? > >> Maybe it's better to remove bus definitions for these chips. > my understanding is that devicetree describes the hardware > so if there's a bus in hardware (that we know about) then we should > describe it in devicetree > > personally I think busses also make the .dts easier to read: > instead of a huge .dts with all nodes on one level it's split into > multiple smaller sub-nodes - thus making it easier to keep track of > "where am I in this file". > OK, I will add the bus description for A1. Thank you for your suggestion. > > Martin > > . >