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Wysocki" , Lukas Wunner Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20260213231428.613164-1-sathyanarayanan.kuppuswamy@linux.intel.com> <9b639ed0-1765-4cca-814e-18a1260e01b9@linux.intel.com> <7b4dd756-2ab7-4331-b560-268f9cff0887@linux.intel.com> Content-Language: en-US From: Kuppuswamy Sathyanarayanan In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi, On 2/19/2026 3:09 AM, Rafael J. Wysocki wrote: > On Thu, Feb 19, 2026 at 9:04 AM Lukas Wunner wrote: >> >> On Wed, Feb 18, 2026 at 06:33:15PM +0100, Rafael J. Wysocki wrote: >>> First, keeping the ports in D0 may gate runtime PC10. Does it not? >> >> The Root Port in question is on the PCH. I'm not sure, does keeping a >> PCH Root Port in D0 also prevent PC10 entry or is that only the case >> for Root Ports on the CPU die/tile? > > If it is located in the PCH, it should not gate PC10 if in D0 at least > in theory, but it would be good to verify that. > > Of course, it will still gate S0ix entry through runtime idle, but > that's a bit moot if the platform is unable to enter S0ix through > runtime idle anyway for other reasons (which is quite likely), or if > the power difference between S0ix and PC10 is small. I will gather current PC10 and S0ix numbers. If there is a significant difference between the two power savings, I will implement the pme_is_broken() approach. > >> If this does cause a power regression, the pme_is_broken() approach >> suggested upthread might be a viable alternative. It'll allow the >> Root Port to go to D3hot but will keep interrupts enabled in the >> Slot Control register. > > Sounds reasonable to me. Sounds good. > -- Sathyanarayanan Kuppuswamy Linux Kernel Developer