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Tue, 09 Aug 2022 09:19:45 -0700 (PDT) Received: from [127.0.0.1] ([187.19.239.32]) by smtp.gmail.com with ESMTPSA id t24-20020ab06998000000b00384cd1abe50sm11679888uaq.32.2022.08.09.09.19.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Aug 2022 09:19:45 -0700 (PDT) Date: Tue, 09 Aug 2022 13:19:40 -0300 From: Arnaldo Carvalho de Melo To: Mike Leach , James Clark CC: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, quic_jinlmao@quicinc.com, suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v2_09/13=5D_perf=3A_cs-etm=3A_Update?= =?US-ASCII?Q?_record_event_to_use_new_Trace_ID_protocol?= User-Agent: K-9 Mail for Android In-Reply-To: References: <20220704081149.16797-1-mike.leach@linaro.org> <20220704081149.16797-10-mike.leach@linaro.org> <5e8981b1-1c32-7ef0-0ef9-93799a8c968b@arm.com> Message-ID: <0C948A97-11E6-40DF-8AAE-94E13B4E8BF2@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On August 9, 2022 1:13:15 PM GMT-03:00, Mike Leach wrote: >Hi James > >On Wed, 20 Jul 2022 at 15:41, James Clark wrote= : >> >> >> >> On 04/07/2022 09:11, Mike Leach wrote: >> > Trace IDs are now dynamically allocated=2E >> > >> > Previously used the static association algorithm that is no longer >> > used=2E The 'cpu * 2 + seed' was outdated and broken for systems with= high >> > core counts (>46)=2E as it did not scale and was broken for larger >> > core counts=2E >> > >> > Trace ID is as unknown in AUXINFO record, and the ID / CPU associati= on >> > will now be sent in PERF_RECORD_AUX_OUTPUT_HW_ID record=2E >> > >> > Remove legacy Trace ID allocation algorithm=2E >> > >> > Signed-off-by: Mike Leach >> > --- >> > include/linux/coresight-pmu=2Eh | 19 +++++++------------ >> > tools/include/linux/coresight-pmu=2Eh | 19 +++++++------------ >> >> I usually see mentions that these header updates need to be separate co= mmits >> because they are merged through different trees=2E >> >> > tools/perf/arch/arm/util/cs-etm=2Ec | 21 ++++++++++++--------- >> > 3 files changed, 26 insertions(+), 33 deletions(-) >> > >> > diff --git a/include/linux/coresight-pmu=2Eh b/include/linux/coresigh= t-pmu=2Eh >> > index 4ac5c081af93=2E=2E9f7ee380266b 100644 >> > --- a/include/linux/coresight-pmu=2Eh >> > +++ b/include/linux/coresight-pmu=2Eh >> > @@ -8,7 +8,13 @@ >> > #define _LINUX_CORESIGHT_PMU_H >> > >> > #define CORESIGHT_ETM_PMU_NAME "cs_etm" >> > -#define CORESIGHT_ETM_PMU_SEED 0x10 >> > + >> > +/* >> > + * Metadata now contains an unused trace ID - IDs are transmitted us= ing a >> > + * PERF_RECORD_AUX_OUTPUT_HW_ID record=2E >> > + * Value architecturally defined as reserved in CoreSight=2E >> > + */ >> > +#define CS_UNUSED_TRACE_ID 0x7F >> > >> > /* >> > * Below are the definition of bit offsets for perf option, and work= s as >> > @@ -32,15 +38,4 @@ >> > #define ETM4_CFG_BIT_RETSTK 12 >> > #define ETM4_CFG_BIT_VMID_OPT 15 >> > >> > -static inline int coresight_get_trace_id(int cpu) >> > -{ >> > - /* >> > - * A trace ID of value 0 is invalid, so let's start at some >> > - * random value that fits in 7 bits and go from there=2E Since >> > - * the common convention is to have data trace IDs be I(N) + 1, >> > - * set instruction trace IDs as a function of the CPU number=2E >> > - */ >> > - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); >> > -} >> > - >> > #endif >> > diff --git a/tools/include/linux/coresight-pmu=2Eh b/tools/include/li= nux/coresight-pmu=2Eh >> > index 6c2fd6cc5a98=2E=2E31d007fab3a6 100644 >> > --- a/tools/include/linux/coresight-pmu=2Eh >> > +++ b/tools/include/linux/coresight-pmu=2Eh >> > @@ -8,7 +8,13 @@ >> > #define _LINUX_CORESIGHT_PMU_H >> > >> > #define CORESIGHT_ETM_PMU_NAME "cs_etm" >> > -#define CORESIGHT_ETM_PMU_SEED 0x10 >> > + >> > +/* >> > + * Metadata now contains an unused trace ID - IDs are transmitted us= ing a >> > + * PERF_RECORD_AUX_OUTPUT_HW_ID record=2E >> > + * Value architecturally defined as reserved in CoreSight=2E >> > + */ >> > +#define CS_UNUSED_TRACE_ID 0x7F >> > >> >> minor nit: this isn't used in the kernel so only needs to be defined on= the >> tools side=2E >> > >Unfortunately if the two versions of coresight-pmu=2Eh are different, >the build process for perf throws out a warning=2E So they have to be >identical=2E James is right, don't worry about the warning, kernel stuff can't go via t= he perf-tools tree=2E - Arnaldo > >Thanks > >Mike > >> > /* >> > * Below are the definition of bit offsets for perf option, and work= s as >> > @@ -34,15 +40,4 @@ >> > #define ETM4_CFG_BIT_RETSTK 12 >> > #define ETM4_CFG_BIT_VMID_OPT 15 >> > >> > -static inline int coresight_get_trace_id(int cpu) >> > -{ >> > - /* >> > - * A trace ID of value 0 is invalid, so let's start at some >> > - * random value that fits in 7 bits and go from there=2E Since >> > - * the common convention is to have data trace IDs be I(N) + 1, >> > - * set instruction trace IDs as a function of the CPU number=2E >> > - */ >> > - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); >> > -} >> > - >> > #endif >> > diff --git a/tools/perf/arch/arm/util/cs-etm=2Ec b/tools/perf/arch/ar= m/util/cs-etm=2Ec >> > index 1b54638d53b0=2E=2E2d68e6a722ed 100644 >> > --- a/tools/perf/arch/arm/util/cs-etm=2Ec >> > +++ b/tools/perf/arch/arm/util/cs-etm=2Ec >> > @@ -421,13 +421,16 @@ static int cs_etm_recording_options(struct auxt= race_record *itr, >> > evlist__to_front(evlist, cs_etm_evsel); >> > >> > /* >> > - * In the case of per-cpu mmaps, we need the CPU on the >> > - * AUX event=2E We also need the contextID in order to be noti= fied >> > + * get the CPU on the sample - need it to associate trace ID in= the >> > + * AUX_OUTPUT_HW_ID event, and the AUX event for per-cpu mmaps= =2E >> > + */ >> > + evsel__set_sample_bit(cs_etm_evsel, CPU); >> > + >> > + /* >> > + * Also the case of per-cpu mmaps, need the contextID in order = to be notified >> > * when a context switch happened=2E >> > */ >> > if (!perf_cpu_map__empty(cpus)) { >> > - evsel__set_sample_bit(cs_etm_evsel, CPU); >> > - >> > err =3D cs_etm_set_option(itr, cs_etm_evsel, >> > BIT(ETM_OPT_CTXTID) | BIT(ETM_O= PT_TS)); >> > if (err) >> > @@ -633,8 +636,9 @@ static void cs_etm_save_etmv4_header(__u64 data[]= , struct auxtrace_record *itr, >> > >> > /* Get trace configuration register */ >> > data[CS_ETMV4_TRCCONFIGR] =3D cs_etmv4_get_config(itr); >> > - /* Get traceID from the framework */ >> > - data[CS_ETMV4_TRCTRACEIDR] =3D coresight_get_trace_id(cpu); >> > + /* traceID set to unused */ >> > + data[CS_ETMV4_TRCTRACEIDR] =3D CS_UNUSED_TRACE_ID; >> > + >> > /* Get read-only information from sysFS */ >> > data[CS_ETMV4_TRCIDR0] =3D cs_etm_get_ro(cs_etm_pmu, cpu, >> > metadata_etmv4_ro[CS_ETM= V4_TRCIDR0]); >> > @@ -681,9 +685,8 @@ static void cs_etm_get_metadata(int cpu, u32 *off= set, >> > magic =3D __perf_cs_etmv3_magic; >> > /* Get configuration register */ >> > info->priv[*offset + CS_ETM_ETMCR] =3D cs_etm_get_confi= g(itr); >> > - /* Get traceID from the framework */ >> > - info->priv[*offset + CS_ETM_ETMTRACEIDR] =3D >> > - coresight_get_trace_id(= cpu); >> > + /* traceID set to unused */ >> > + info->priv[*offset + CS_ETM_ETMTRACEIDR] =3D CS_UNUSED_= TRACE_ID; >> > /* Get read-only information from sysFS */ >> > info->priv[*offset + CS_ETM_ETMCCER] =3D >> > cs_etm_get_ro(cs_etm_pmu, cpu, > > >