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charset="utf-8" CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220219175832epcas5p399b652e6da610ada233376651694b42c References: <20220219181003.12739-1-alim.akhtar@samsung.com> <72848f6c-adc7-2d36-edcd-9a5fac655bbc@canonical.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >-----Original Message----- >From: Krzysztof Kozlowski =5Bmailto:krzysztof.kozlowski=40canonical.com=5D >Sent: Sunday, February 20, 2022 3:32 PM >To: Alim Akhtar ; linux-arm- >kernel=40lists.infradead.org; linux-kernel=40vger.kernel.org >Cc: linux-samsung-soc=40vger.kernel.org; daniel.lezcano=40linaro.org; >tglx=40linutronix.de; pankaj.dubey=40samsung.com; >m.szyprowski=40samsung.com >Subject: Re: =5BPATCH=5D clocksource/drivers/exynos_mct: Remove mct interr= upt >index enum > >On 19/02/2022 19:10, Alim Akhtar wrote: >> MCT driver define an enum which list global and local timer's irq >> index. Most of them are not used but MCT_G0_IRQ and MCT_L0_IRQ and >> these two are at a fixed offset/index. >> Get rid of this enum and use a =23define for the used irq index. >> >> While at it, bump-up maximum number of MCT IRQ to match the binding >> documentation. And also change the name variable to be more generic. >> >> No functional changes expected. > >There is a functional change - you increase MCT_NR_IRQS from 12 to 20 whic= h >affects size of mct_irqs. Can you increase it in separate commit? > Yes, my thought was it is going to increase the mct_irqs array size and it = will not affect any=20 of the current SoC's mct functionality. Anyway, I will separate it out as you suggested. >> >> Signed-off-by: Alim Akhtar >> --- >> drivers/clocksource/exynos_mct.c =7C 25 ++++++++----------------- >> 1 file changed, 8 insertions(+), 17 deletions(-) >> >> - currently tested on exynos7 platform, appreciate testing on >> exynos-=7B3,4,5=7D platforms >> >> diff --git a/drivers/clocksource/exynos_mct.c >> b/drivers/clocksource/exynos_mct.c >> index 6db3d5511b0f..4aea9cd3f7ba 100644 >> --- a/drivers/clocksource/exynos_mct.c >> +++ b/drivers/clocksource/exynos_mct.c >> =40=40 -60,27 +60,18 =40=40 >> =23define MCT_CLKEVENTS_RATING 350 >> =23endif >> >> +/* There are four Global timers starting with 0 offset */ >> +=23define MCT_G0_IRQ 0 >> +/* Local timers count starts after global timer count */ >> +=23define MCT_L0_IRQ 4 >> +/* Max number of MCT IRQ as per binding document */ >> +=23define MCT_NR_IRQS 20 >> + >> enum =7B >> MCT_INT_SPI, >> MCT_INT_PPI >> =7D; >> >> -enum =7B >> - MCT_G0_IRQ, >> - MCT_G1_IRQ, >> - MCT_G2_IRQ, >> - MCT_G3_IRQ, >> - MCT_L0_IRQ, >> - MCT_L1_IRQ, >> - MCT_L2_IRQ, >> - MCT_L3_IRQ, >> - MCT_L4_IRQ, >> - MCT_L5_IRQ, >> - MCT_L6_IRQ, >> - MCT_L7_IRQ, >> - MCT_NR_IRQS, >> -=7D; >> - >> static void __iomem *reg_base; >> static unsigned long clk_rate; >> static unsigned int mct_int_type; >> =40=40 -89,7 +80,7 =40=40 static int mct_irqs=5BMCT_NR_IRQS=5D; struct >> mct_clock_event_device =7B >> struct clock_event_device evt; >> unsigned long base; >> - char name=5B10=5D; >> + char name=5BMCT_NR_IRQS - 1=5D; > >This does not look related MCT_NR_IRQS and using here MCT_NR_IRQS >confuses. This is a =22mct_tick%d=22 with number of local timers, so maybe= make >it just 11? > Yes, it is for local timer, let me add separate macro for this, which match= es the current dt binding. As per binding max 16 local timers can be supported.=20 And it will make code scalable, which is the positive side effect of this c= hange. >> =7D; >> >> static void exynos4_mct_write(unsigned int value, unsigned long >> offset) > > >Best regards, >Krzysztof