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Tue, 8 Dec 2020 04:42:18 -0800 Envelope-to: michal.simek@xilinx.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, quanyang.wang@windriver.com Received: from [172.30.17.109] (port=43702) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kmcJt-0001dS-VW; Tue, 08 Dec 2020 04:42:18 -0800 Subject: Re: [PATCH] clk: zynqmp: enable COMMON_CLK_ZYNQMP for ARCH_ZYNQMP automatically To: , , , CC: , , References: <20201208123508.998073-1-quanyang.wang@windriver.com> From: Michal Simek Message-ID: <0a0d16a7-0d49-3a89-76a1-141758b138e7@xilinx.com> Date: Tue, 8 Dec 2020 13:42:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.1 MIME-Version: 1.0 In-Reply-To: <20201208123508.998073-1-quanyang.wang@windriver.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ca24bfc4-124c-44ad-5d25-08d89b76b32c X-MS-TrafficTypeDiagnostic: CY4PR0201MB3572: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2020 12:42:18.6780 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca24bfc4-124c-44ad-5d25-08d89b76b32c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT030.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR0201MB3572 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 08. 12. 20 13:35, quanyang.wang@windriver.com wrote: > From: Quanyang Wang > > The Zynqmp Ultrascale clock controller generates clocks for peripherals, > so we need to enable it when ARCH_ZYNQMP is selected. > > Signed-off-by: Quanyang Wang > --- > drivers/clk/zynqmp/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/zynqmp/Kconfig b/drivers/clk/zynqmp/Kconfig > index 17086059be8b..a8aa58bbb790 100644 > --- a/drivers/clk/zynqmp/Kconfig > +++ b/drivers/clk/zynqmp/Kconfig > @@ -4,6 +4,7 @@ config COMMON_CLK_ZYNQMP > bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers" > depends on ARCH_ZYNQMP || COMPILE_TEST > depends on ZYNQMP_FIRMWARE > + default ARCH_ZYNQMP This is not right. If you look 2 lines above. > help > Support for the Zynqmp Ultrascale clock controller. > It has a dependency on the PMU firmware. > And we were talking about enabling this driver in defconfig. Not via Kconfig. This fragment was designed in a way that this clock controller doesn't need to be used. It is our default but if you want to use for example fixed clock you also can. This enables space for being able to use for example different firmware. Thanks, Michal