From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3558FCCA480 for ; Mon, 11 Jul 2022 06:50:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229687AbiGKGup (ORCPT ); Mon, 11 Jul 2022 02:50:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229517AbiGKGun (ORCPT ); Mon, 11 Jul 2022 02:50:43 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAB8115811; Sun, 10 Jul 2022 23:50:42 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 68E8361224; Mon, 11 Jul 2022 06:50:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C313CC34115; Mon, 11 Jul 2022 06:50:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657522241; bh=v728tOul6+PGvXrlWjEPs+tZZnXRsqYiqEgFBvOFrZI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DoMmBTYW8sPb35KHgtw0eHES3TzliwEXBMid+Er6yW7PN6LffQGW0I2rK4eT0+J6S bElViG2seshFAVqYqC7o2IWawrRk8hGlRXjUO/EKy5kacJMhZodBBaBzjq4SUErPA7 gfQRINGyMZ9eFmoATYvosmEWRKAOtxLLmeZ4UH3P/r1LmLk1vxqB6SZf2emCLpLuIp hdVTqKBK9HyNp5buRj+Gmx+snS1l9P7X39ZDplz9VGihU44AWX2ASllVW/bhaT/W0q oBDhH6P2i7GHi5Q/wKtforE4YWOdkI8wwc6xqNCK43s6FnMcoxqX8nvNJvG27nHOSP VzVvvz/OVt+Cg== Received: from mchehab by mail.kernel.org with local (Exim 4.95) (envelope-from ) id 1oAnFe-004a3P-HD; Mon, 11 Jul 2022 07:50:38 +0100 From: Mauro Carvalho Chehab Cc: Chris Wilson , "Tvrtko Ursulin" , Andi Shyti , Daniel Vetter , Daniele Ceraolo Spurio , Dave Airlie , David Airlie , Jani Nikula , John Harrison , Joonas Lahtinen , Lucas De Marchi , Matt Roper , Rodrigo Vivi , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Mauro Carvalho Chehab , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= Subject: [PATCH v4 2/2] drm/i915/gt: Serialize TLB invalidates with GT resets Date: Mon, 11 Jul 2022 07:50:37 +0100 Message-Id: <0a5f5bca4a9f538a8529a1496c3dd3453268a69a.1657522157.git.mchehab@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chris Wilson Avoid trying to invalidate the TLB in the middle of performing an engine reset, as this may result in the reset timing out. Currently, the TLB invalidate is only serialised by its own mutex, forgoing the uncore lock, but we can take the uncore->lock as well to serialise the mmio access, thereby serialising with the GDRST. Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with i915 selftest/hangcheck. Cc: stable@vger.kernel.org # v4.4 and upper Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") Reported-by: Mauro Carvalho Chehab Tested-by: Mauro Carvalho Chehab Reviewed-by: Mauro Carvalho Chehab Cc: Tvrtko Ursulin Reviewed-by: Andi Shyti Acked-by: Thomas Hellström Signed-off-by: Mauro Carvalho Chehab --- See [PATCH v4 0/2] at: https://lore.kernel.org/all/cover.1657522157.git.mchehab@kernel.org/ drivers/gpu/drm/i915/gt/intel_gt.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 8da3314bb6bf..68c2b0d8f187 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -952,6 +952,20 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) mutex_lock(>->tlb_invalidate_lock); intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); + spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */ + + for_each_engine(engine, gt, id) { + struct reg_and_bit rb; + + rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); + if (!i915_mmio_reg_offset(rb.reg)) + continue; + + intel_uncore_write_fw(uncore, rb.reg, rb.bit); + } + + spin_unlock_irq(&uncore->lock); + for_each_engine(engine, gt, id) { /* * HW architecture suggest typical invalidation time at 40us, @@ -966,7 +980,6 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) if (!i915_mmio_reg_offset(rb.reg)) continue; - intel_uncore_write_fw(uncore, rb.reg, rb.bit); if (__intel_wait_for_register_fw(uncore, rb.reg, rb.bit, 0, timeout_us, timeout_ms, -- 2.36.1