From: Christophe Leroy <christophe.leroy@csgroup.eu>
To: Ravi Bangoria <ravi.bangoria@linux.ibm.com>,
mpe@ellerman.id.au, christophe.leroy@c-s.fr
Cc: mikey@neuling.org, paulus@samba.org,
naveen.n.rao@linux.vnet.ibm.com, pedromfc@linux.ibm.com,
rogealve@linux.ibm.com, jniethe5@gmail.com,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 4/8] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c
Date: Tue, 25 Aug 2020 11:30:15 +0200 [thread overview]
Message-ID: <0a73280b-c231-a7bb-18d9-abf2a37ba24b@csgroup.eu> (raw)
In-Reply-To: <20200825043617.1073634-5-ravi.bangoria@linux.ibm.com>
Le 25/08/2020 à 06:36, Ravi Bangoria a écrit :
> Power10 hw has multiple DAWRs but hw doesn't tell which DAWR caused
> the exception. So we have a sw logic to detect that in hw_breakpoint.c.
> But hw_breakpoint.c gets compiled only with CONFIG_HAVE_HW_BREAKPOINT=Y.
> Move DAWR detection logic outside of hw_breakpoint.c so that it can be
> reused when CONFIG_HAVE_HW_BREAKPOINT is not set.
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
> ---
> arch/powerpc/include/asm/hw_breakpoint.h | 8 +
> arch/powerpc/kernel/Makefile | 3 +-
> arch/powerpc/kernel/hw_breakpoint.c | 159 +----------------
> .../kernel/hw_breakpoint_constraints.c | 162 ++++++++++++++++++
> 4 files changed, 174 insertions(+), 158 deletions(-)
> create mode 100644 arch/powerpc/kernel/hw_breakpoint_constraints.c
>
[...]
> diff --git a/arch/powerpc/kernel/hw_breakpoint_constraints.c b/arch/powerpc/kernel/hw_breakpoint_constraints.c
> new file mode 100644
> index 000000000000..867ee4aa026a
> --- /dev/null
> +++ b/arch/powerpc/kernel/hw_breakpoint_constraints.c
> @@ -0,0 +1,162 @@
[...]
> +
> +static int cache_op_size(void)
> +{
> +#ifdef __powerpc64__
> + return ppc64_caches.l1d.block_size;
> +#else
> + return L1_CACHE_BYTES;
> +#endif
> +}
You've got l1_dcache_bytes() in arch/powerpc/include/asm/cache.h to do that.
> +
> +void wp_get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
> + int *type, int *size, unsigned long *ea)
> +{
> + struct instruction_op op;
> +
> + if (__get_user_instr_inatomic(*instr, (void __user *)regs->nip))
> + return;
> +
> + analyse_instr(&op, regs, *instr);
> + *type = GETTYPE(op.type);
> + *ea = op.ea;
> +#ifdef __powerpc64__
> + if (!(regs->msr & MSR_64BIT))
> + *ea &= 0xffffffffUL;
> +#endif
This #ifdef is unneeded, it should build fine on a 32 bits too.
> +
> + *size = GETSIZE(op.type);
> + if (*type == CACHEOP) {
> + *size = cache_op_size();
> + *ea &= ~(*size - 1);
> + } else if (*type == LOAD_VMX || *type == STORE_VMX) {
> + *ea &= ~(*size - 1);
> + }
> +}
>
Christophe
next prev parent reply other threads:[~2020-08-25 9:30 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-25 4:36 [PATCH v5 0/8] powerpc/watchpoint: Bug fixes plus new feature flag Ravi Bangoria
2020-08-25 4:36 ` [PATCH v5 1/8] powerpc/watchpoint: Fix quarword instruction handling on p10 predecessors Ravi Bangoria
2020-08-25 4:36 ` [PATCH v5 2/8] powerpc/watchpoint: Fix handling of vector instructions Ravi Bangoria
2020-08-25 4:36 ` [PATCH v5 3/8] powerpc/watchpoint/ptrace: Fix SETHWDEBUG when CONFIG_HAVE_HW_BREAKPOINT=N Ravi Bangoria
2020-08-25 4:36 ` [PATCH v5 4/8] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c Ravi Bangoria
2020-08-25 9:30 ` Christophe Leroy [this message]
2020-08-25 11:08 ` Ravi Bangoria
2020-08-25 11:48 ` Christophe Leroy
2020-08-25 4:36 ` [PATCH v5 5/8] powerpc/watchpoint: Fix exception handling for CONFIG_HAVE_HW_BREAKPOINT=N Ravi Bangoria
2020-08-25 9:37 ` Christophe Leroy
2020-08-25 11:07 ` Ravi Bangoria
2020-08-25 12:06 ` Christophe Leroy
2020-08-25 4:36 ` [PATCH v5 6/8] powerpc/watchpoint: Add hw_len wherever missing Ravi Bangoria
2020-08-25 4:36 ` [PATCH v5 7/8] powerpc/watchpoint/ptrace: Introduce PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 Ravi Bangoria
2020-08-25 4:36 ` [PATCH v5 8/8] powerpc/watchpoint/selftests: Tests for kernel accessing user memory Ravi Bangoria
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