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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Dqo+pHJo3wp/7kesweI0iFqum7wodilp2hSK4UUvEzN5X5LJXEjh0WsgrpuIYwEEqxglMSu+GRhbDuk9jPdt4iiQq7LAnNxi03xQSF/WUr/QLUpBvhQ1kmjrH8+xfxu6VVKhC8G9ndRmG9zdSmKthOzj3+619XGrWHU1zdb04j4Lctc77zN25b/zvlhQY9kXp5gt9Haic+XSgl9Ka2dg5PwrSS7wE9a9t1Jma3IRAmZqgant0Luuf5R4hjvqANvctf6upi1crjOMYNrFLEAIYNanaPTFxZ7hryqaiqDLy/zLlzONiPW5Nx5rEmE3usdEaa85K8zAODUn8aHQAvXKhLDbH+Sat5U1lpucxQ2pHGXvFATvcr+Aom0bmsSdeJ2TddY3yDnC3j4FClubdrDD7RB2A2YNpln+BGudiyD8mNDimB8IxZaTlcsA1jdqwL8l X-OriginatorOrg: topic.nl X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2026 13:45:00.5549 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b01d0eed-d53a-4a99-b4a7-08de94abdd4b X-MS-Exchange-CrossTenant-Id: 449607a5-3517-482d-8d16-41dd868cbda3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=449607a5-3517-482d-8d16-41dd868cbda3;Ip=[20.93.157.195];Helo=[westeu11-emailsignatures-cloud.codetwo.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001AB.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR04MB11065 On 07-04-2026 14:59, Francesco Lavra wrote: > On Tue, 2026-04-07 at 12:17 +0200, Mike Looijmans wrote: >> On 07-04-2026 08:58, Linus Walleij wrote: >>> On Mon, Mar 30, 2026 at 6:19=E2=80=AFPM Francesco Lavra >>> wrote: >>> >>>> A chip being probed may have the interrupt-on-change feature enabled >>>> on >>>> some of its pins, for example after a reboot. This can cause the chip >>>> to >>>> generate interrupts for pins that don't have a registered nested >>>> handler, >>>> which leads to a kernel crash such as below: >>>> >>>> [=C2=A0=C2=A0=C2=A0 7.928897] Unable to handle kernel read from unread= able memory at >>>> virtual address 00000000000000ac >>>> [=C2=A0=C2=A0=C2=A0 7.932314] Mem abort info: >>>> [=C2=A0=C2=A0=C2=A0 7.935081]=C2=A0=C2=A0 ESR =3D 0x0000000096000004 >>>> [=C2=A0=C2=A0=C2=A0 7.938808]=C2=A0=C2=A0 EC =3D 0x25: DABT (current E= L), IL =3D 32 bits >>>> [=C2=A0=C2=A0=C2=A0 7.944094]=C2=A0=C2=A0 SET =3D 0, FnV =3D 0 >>>> [=C2=A0=C2=A0=C2=A0 7.947127]=C2=A0=C2=A0 EA =3D 0, S1PTW =3D 0 >>>> [=C2=A0=C2=A0=C2=A0 7.950247]=C2=A0=C2=A0 FSC =3D 0x04: level 0 transl= ation fault >>>> [=C2=A0=C2=A0=C2=A0 7.955101] Data abort info: >>>> [=C2=A0=C2=A0=C2=A0 7.957961]=C2=A0=C2=A0 ISV =3D 0, ISS =3D 0x0000000= 4, ISS2 =3D 0x00000000 >>>> [=C2=A0=C2=A0=C2=A0 7.963421]=C2=A0=C2=A0 CM =3D 0, WnR =3D 0, TnD =3D= 0, TagAccess =3D 0 >>>> [=C2=A0=C2=A0=C2=A0 7.968447]=C2=A0=C2=A0 GCS =3D 0, Overlay =3D 0, Di= rtyBit =3D 0, Xs =3D 0 >>>> [=C2=A0=C2=A0=C2=A0 7.973734] user pgtable: 4k pages, 48-bit VAs, >>>> pgdp=3D00000000089b7000 >>>> [=C2=A0=C2=A0=C2=A0 7.980148] [00000000000000ac] pgd=3D000000000000000= 0, >>>> p4d=3D0000000000000000 >>>> [=C2=A0=C2=A0=C2=A0 7.986913] Internal error: Oops: 0000000096000004 [= #1]=C2=A0 SMP >>>> [=C2=A0=C2=A0=C2=A0 7.992545] Modules linked in: >>>> [=C2=A0=C2=A0=C2=A0 8.073678] CPU: 0 UID: 0 PID: 81 Comm: irq/18-4-002= 5 Not tainted >>>> 7.0.0-rc6-gd2b5a1f931c8-dirty #199 >>>> [=C2=A0=C2=A0=C2=A0 8.073689] Hardware name: Khadas VIM3 (DT) >>>> [=C2=A0=C2=A0=C2=A0 8.073692] pstate: 604000c5 (nZCv daIF +PAN -UAO -T= CO -DIT -SSBS >>>> BTYPE=3D--) >>>> [=C2=A0=C2=A0=C2=A0 8.094639] pc : _raw_spin_lock_irq+0x40/0x80 >>>> [=C2=A0=C2=A0=C2=A0 8.098970] lr : handle_nested_irq+0x2c/0x168 >>>> [=C2=A0=C2=A0=C2=A0 8.098979] sp : ffff800082b2bd20 >>>> [=C2=A0=C2=A0=C2=A0 8.106599] x29: ffff800082b2bd20 x28: ffff800080107= 920 x27: >>>> ffff800080104d88 >>>> [=C2=A0=C2=A0=C2=A0 8.106611] x26: ffff000003298080 x25: 0000000000000= 001 x24: >>>> 000000000000ff00 >>>> [=C2=A0=C2=A0=C2=A0 8.113707] x23: 0000000000000001 x22: 0000000000000= 000 x21: >>>> 000000000000000e >>>> [=C2=A0=C2=A0=C2=A0 8.120850] x20: 0000000000000000 x19: 0000000000000= 0ac x18: >>>> 0000000000000000 >>>> [=C2=A0=C2=A0=C2=A0 8.135046] x17: 0000000000000000 x16: 0000000000000= 000 x15: >>>> 0000000000000000 >>>> [=C2=A0=C2=A0=C2=A0 8.135062] x14: ffff800081567ea8 x13: fffffffffffff= fff x12: >>>> 0000000000000000 >>>> [=C2=A0=C2=A0=C2=A0 8.135070] x11: 00000000000000c0 x10: 0000000000000= b60 x9 : >>>> ffff800080109e0c >>>> [=C2=A0=C2=A0=C2=A0 8.135078] x8 : 1fffe0000069dbc1 x7 : 0000000000000= 001 x6 : >>>> ffff0000034ede00 >>>> [=C2=A0=C2=A0=C2=A0 8.135086] x5 : 0000000000000000 x4 : ffff0000034ed= e08 x3 : >>>> 0000000000000001 >>>> [=C2=A0=C2=A0=C2=A0 8.163460] x2 : 0000000000000000 x1 : 0000000000000= 001 x0 : >>>> 00000000000000ac >>>> [=C2=A0=C2=A0=C2=A0 8.170560] Call trace: >>>> [=C2=A0=C2=A0=C2=A0 8.180094]=C2=A0 _raw_spin_lock_irq+0x40/0x80 (P) >>>> [=C2=A0=C2=A0=C2=A0 8.184443]=C2=A0 mcp23s08_irq+0x248/0x358 >>>> [=C2=A0=C2=A0=C2=A0 8.184462]=C2=A0 irq_thread_fn+0x34/0xb8 >>>> [=C2=A0=C2=A0=C2=A0 8.184470]=C2=A0 irq_thread+0x1a4/0x310 >>>> [=C2=A0=C2=A0=C2=A0 8.195093]=C2=A0 kthread+0x13c/0x150 >>>> [=C2=A0=C2=A0=C2=A0 8.198309]=C2=A0 ret_from_fork+0x10/0x20 >>>> [=C2=A0=C2=A0=C2=A0 8.201850] Code: d65f03c0 d2800002 52800023 f980001= 1 (885ffc01) >>>> [=C2=A0=C2=A0=C2=A0 8.207931] ---[ end trace 0000000000000000 ]--- >>>> >>>> This issue has always been present, but has been latent until commit >>>> "f9f4fda15e72" ("pinctrl: mcp23s08: init reg_defaults from HW at >>>> probe and >>>> switch cache type"), which correctly removed reg_defaults from the >>>> regmap >>>> and as a side effect changed the behavior of the interrupt handler so >>>> that >>>> the real value of the MCP_GPINTEN register is now being read from the >>>> chip >>>> instead of using a bogus 0 default value; a non-zero value for this >>>> register can trigger the invocation of a nested handler which may not >>>> exist >>>> (yet). >>>> Fix this issue by disabling all pin interrupts during initialization. >>>> >>>> Fixes: "f9f4fda15e72" ("pinctrl: mcp23s08: init reg_defaults from HW >>>> at probe and switch cache type") >>>> Signed-off-by: Francesco Lavra >>> Patch applied for fixes since it's pretty urgent, and it also looks >>> right to me. >>> >>> However added some people using this to the CC so they >>> get a chance to react before it goes upstream. >> Looks okay to me too. >> >> Maybe it'd be better to unconditionally write "0" to this register? No >> need to exercise the interrupt logic and pins when no-one is listening..= . > Not sure I understand, unconditionally writing "0" to this register is > exactly what this patch does. It appears to be inside a "if (mcp->irq && mcp->irq_controller)" block. Which is fine, of course. If there's no handler, the register has no effect= . I just thought it'd be cleaner to set it to 0 as part of the global=20 initialization at the start of probe. >> I was going to say "if the device doesn't have a reset GPIO", but >> looking at the code, the reset GPIO is never asserted by this driver. > Right. In any case, the reset GPIO is optional, so we would still need to > initialize the register manually if there is no reset GPIO. I suspect it's actually a bug in the driver that it doesn't assert the=20 reset (before de-asserting). But that's for another patch... --=20 Mike Looijmans System Expert TOPIC Embedded Products B.V. Materiaalweg 4, 5681 RJ Best The Netherlands T: +31 (0) 499 33 69 69 E: mike.looijmans@topic.nl W: www.topic.nl