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Sat, 14 Nov 2026 16:59:21 -0800 (PST) Received: from [192.168.35.43] ([218.50.238.131]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-379508762a5sm20244703eec.0.2026.11.14.16.59.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Nov 2026 16:59:21 -0800 (PST) Message-ID: <0a8c0d90-9d80-4688-83b3-faf6bf04ca06@gmail.com> Date: Sun, 15 Nov 2026 09:59:16 +0900 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: chanwoo@kernel.org Subject: Re: [PATCH v2 5/7] PM / devfreq: rockchip-dfi: move register offsets to variant struct Content-Language: ko To: Sebastian Reichel , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Sascha Hauer Cc: Nicolas Frattaroli , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kernel@collabora.com References: <20260921-b4-rockchip-dfi-rk3576-support-v2-0-04f847016321@collabora.com> <20260921-b4-rockchip-dfi-rk3576-support-v2-5-04f847016321@collabora.com> From: Choi Chanwoo In-Reply-To: <20260921-b4-rockchip-dfi-rk3576-support-v2-5-04f847016321@collabora.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/22/2026 6:15 AM, Sebastian Reichel wrote: > DDRMON in version 0x40 (found in RK3576) has two control registers, > which moves the register addresses. Move the register offsets from the > defines to the varaint struct to ease supporting the newer version. > > Signed-off-by: Sebastian Reichel > --- > drivers/devfreq/event/rockchip-dfi.c | 34 ++++++++++++++++++++++++---------- > 1 file changed, 24 insertions(+), 10 deletions(-) > > diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c > index 380361a231a2..8490219f61be 100644 > --- a/drivers/devfreq/event/rockchip-dfi.c > +++ b/drivers/devfreq/event/rockchip-dfi.c > @@ -42,12 +42,6 @@ > #define DDRMON_CTRL_TIMER_CNT_EN BIT(0) > #define DDRMON_CTRL_LP5_BANK_MODE_MASK GENMASK(8, 7) > > -#define DDRMON_CH0_WR_NUM 0x20 > -#define DDRMON_CH0_RD_NUM 0x24 > -#define DDRMON_CH0_COUNT_NUM 0x28 > -#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c > -#define DDRMON_CH1_COUNT_NUM 0x3c > -#define DDRMON_CH1_DFI_ACCESS_NUM 0x40 > > #define PERF_EVENT_CYCLES 0x0 > #define PERF_EVENT_READ_BYTES 0x1 > @@ -128,6 +122,10 @@ struct rockchip_dfi { > * @clocks_optional: whether not finding the clocks is non-fatal. Set if the > * DT binding for this variant didn't require clocks in the > * past, so that the driver remains compatible with old DTs. > + * @reg_write_access: register offset for writes access > + * @reg_read_access: register offset for read access > + * @reg_access: register offset for read/write access > + * @reg_clock_cycles: register offset for clock cycles > */ > struct rockchip_dfi_variant { > int (*init)(struct rockchip_dfi *dfi); > @@ -137,6 +135,10 @@ struct rockchip_dfi_variant { > const char * const *clk_names; > unsigned int num_clks; > bool clocks_optional; > + u8 reg_write_access; > + u8 reg_read_access; > + u8 reg_access; > + u8 reg_clock_cycles; > }; > > static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctrl) > @@ -275,13 +277,13 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun > if (!(dfi->channel_mask & BIT(i))) > continue; > res->c[i].read_access = readl_relaxed(dfi_regs + > - DDRMON_CH0_RD_NUM + i * dfi->variant->stride); > + dfi->variant->reg_read_access + i * dfi->variant->stride); > res->c[i].write_access = readl_relaxed(dfi_regs + > - DDRMON_CH0_WR_NUM + i * dfi->variant->stride); > + dfi->variant->reg_write_access + i * dfi->variant->stride); > res->c[i].access = readl_relaxed(dfi_regs + > - DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->variant->stride); > + dfi->variant->reg_access + i * dfi->variant->stride); > res->c[i].clock_cycles = readl_relaxed(dfi_regs + > - DDRMON_CH0_COUNT_NUM + i * dfi->variant->stride); > + dfi->variant->reg_clock_cycles + i * dfi->variant->stride); > } > } > > @@ -829,6 +831,10 @@ static const struct rockchip_dfi_variant rk3399_variant = { > .max_channels = 2, > .clk_names = rk3399_clk_names, > .num_clks = ARRAY_SIZE(rk3399_clk_names), > + .reg_write_access = 0x20, > + .reg_read_access = 0x24, > + .reg_clock_cycles = 0x28, > + .reg_access = 0x2c, > }; > > static const struct rockchip_dfi_variant rk3568_variant = { > @@ -836,6 +842,10 @@ static const struct rockchip_dfi_variant rk3568_variant = { > .stride = 0x0, > .ctrl_single = true, > .max_channels = 1, > + .reg_write_access = 0x20, > + .reg_read_access = 0x24, > + .reg_clock_cycles = 0x28, > + .reg_access = 0x2c, > }; > > static const struct rockchip_dfi_variant rk3588_variant = { > @@ -845,6 +855,10 @@ static const struct rockchip_dfi_variant rk3588_variant = { > .clk_names = rk3588_clk_names, > .num_clks = ARRAY_SIZE(rk3588_clk_names), > .clocks_optional = true, > + .reg_write_access = 0x20, > + .reg_read_access = 0x24, > + .reg_clock_cycles = 0x28, > + .reg_access = 0x2c, > }; > > static const struct of_device_id rockchip_dfi_id_match[] = { > Acked-by: Chanwoo Choi -- Best Regards, Chanwoo Choi Principal Engineer, Samsung Electronics