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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-64092e1a405sm7542470a12.31.2025.11.03.03.44.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Nov 2025 03:44:45 -0800 (PST) Message-ID: <0ab3c556-8876-4598-a7d5-ba7f9eb33391@oss.qualcomm.com> Date: Mon, 3 Nov 2025 12:44:41 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] drm/msm/a6xx: Add support for Adreno 612 To: Akhil P Oommen , rob.clark@oss.qualcomm.com Cc: Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jie Zhang References: <20251017-qcs615-spin-2-v1-0-0baa44f80905@oss.qualcomm.com> <20251017-qcs615-spin-2-v1-1-0baa44f80905@oss.qualcomm.com> <44ff81bf-8970-475c-a4f5-c03220bc8c3f@oss.qualcomm.com> <97aeb6a1-fda2-440f-b14b-2f3dbc2d7e8e@oss.qualcomm.com> <5e64c246-a424-42c9-b102-e1a2af579936@oss.qualcomm.com> <7c563e83-031c-445c-bcfa-c04f4729622d@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <7c563e83-031c-445c-bcfa-c04f4729622d@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=P7Q3RyAu c=1 sm=1 tr=0 ts=690895af cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=IwubUePDlzt84yfe0skA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: ILgNC6aecqeT5011JKaxC0uuxCmiR-0V X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTAzMDEwNiBTYWx0ZWRfXx/s1NeXdzgl7 6uybqo+ABVKnLI7XBizt/tcDWKC/2dTF0i3hq3ujNiOHn0iqyU/m240xvmERIvpnU9j9E1BeUQm P9UxYBxmdp15IPEKXKNb9JCyza8K2UrjGoQvkxhrin6U5XdYk2jRttpUQBQefsgzMLxaFAy7MYt 3x77ciiPfaJug0eH4Q0B5eDsZoZoxxWFLtQj+UpYmqrd6CWHhWI1ysVXPfoSdwO5sZn+GfWU3La x1Oh0oshZExPmcvs5Tl/zWAn/EG4d/Z1fLd/SiTN/XL7R0cBl+n0qzTe1opso+QuLhtkP1cbHqn xNeM9UnCp38TkgqatLuZGkyOZI1Gl/N7SdcLzaPLwtmnWVOdLbUPFA6Op8u/8mwLR92JF09hjGp H5N+O7NEmbuxvPXXvas6dKnV2MeurQ== X-Proofpoint-ORIG-GUID: ILgNC6aecqeT5011JKaxC0uuxCmiR-0V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-03_01,2025-11-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 phishscore=0 clxscore=1015 suspectscore=0 adultscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511030106 On 10/24/25 4:23 PM, Akhil P Oommen wrote: > On 10/24/2025 6:46 PM, Rob Clark wrote: >> On Fri, Oct 24, 2025 at 12:55 AM Konrad Dybcio >> wrote: >>> >>> On 10/24/25 12:57 AM, Akhil P Oommen wrote: >>>> On 10/22/2025 8:43 PM, Konrad Dybcio wrote: >>>>> On 10/17/25 7:08 PM, Akhil P Oommen wrote: >>>>>> From: Jie Zhang >>>>>> >>>>>> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. >>>>>> A612 falls under ADRENO_6XX_GEN1 family and is a cut down version >>>>>> of A615 GPU. >>>>>> >>>>>> A612 has a new IP called Reduced Graphics Management Unit or RGMU >>>>>> which is a small state machine which helps to toggle GX GDSC >>>>>> (connected to CX rail) to implement IFPC feature. It doesn't support >>>>>> any other features of a full fledged GMU like clock control, resource >>>>>> voting to rpmh etc. So we need linux clock driver support like other >>>>>> gmu-wrapper implementations to control gpu core clock and gpu GX gdsc. >>>>>> This patch skips RGMU core initialization and act more like a >>>>>> gmu-wrapper case. >>>>>> >>>>>> Co-developed-by: Akhil P Oommen >>>>>> Signed-off-by: Jie Zhang >>>>>> Signed-off-by: Akhil P Oommen >>>>>> --- >>>>> >>>>> [...] >>>>> >>>>>> @@ -350,12 +350,18 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { >>>>>> /* Trigger a OOB (out of band) request to the GMU */ >>>>>> int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) >>>>>> { >>>>>> + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); >>>>>> + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; >>>>>> int ret; >>>>>> u32 val; >>>>>> int request, ack; >>>>>> >>>>>> WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); >>>>>> >>>>>> + /* Skip OOB calls since RGMU is not enabled */ >>>>> >>>>> "RGMU doesn't handle OOB calls" >>>> >>>> Technically RGMU can handle OOB calls. But we are not initializing rgmu. >>> >>> Oh, I glossed over that.. >>> >>> IIRC the reason we delayed 612 support in the past was to make sure >>> that the RGMU FW is consumed, so that runtime requirements don't >>> suddenly change one day. >>> >>> If you have no interest/way in getting it wholly supported right now, >>> can you at least make sure that the driver requests the firmware and >>> exits if it's absent? >> >> adreno_load_gpu() calls adreno_load_fw() first thing, and will bail if >> gmu fw is missing. (zap fw is a bit more awkward since that could >> come from dt or device table.) > > Correct. And RGMU firmware is available in linux-firmware repo. Thanks! Konrad