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Thu, 2 Jul 2026 21:07:48 -0700 From: Nicolin Chen To: Will Deacon , Robin Murphy , "Joerg Roedel" , Bjorn Helgaas , "Jason Gunthorpe" CC: "Rafael J . Wysocki" , Len Brown , Pranjal Shrivastava , Mostafa Saleh , Lu Baolu , Kevin Tian , , , , , , , Shuai Xue Subject: [PATCH v5 12/18] iommu/arm-smmu-v3: Introduce arm_smmu_cmdq_batch_issue() wrapper Date: Thu, 2 Jul 2026 21:06:37 -0700 Message-ID: <0abc2e92551aeb483091a975915eb5dfe07dc007.1783044582.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150B:EE_|CY5PR12MB6575:EE_ X-MS-Office365-Filtering-Correlation-Id: 09545dc1-9ae6-416f-e46c-08ded8b8aeb5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|82310400026|1800799024|376014|23010399003|3023799007|11063799006|18002099003|22082099003|56012099006; X-Microsoft-Antispam-Message-Info: OR2CN3ty9vBEvBHFbt8A5xR7jGLi9TF7PEQ9P1lLAT5IPR+tHOjMqmr7/SPaqYevTqfQnp0YWTmfO8WqcfkrXgROJEtNHfqTHCqu4AzOpxaQ/AKWywoZCT9oB7cC3d95O8vuAmIZg8kdCGx9DKtXoXfvglOEu3fERCAZVeJk3XxX+j1UxF4GLeIwdMIy208CBPImF7kX7uJr/4rjhSNNaj39d5FLWSBEaPPAq3dq1HPwpv0iEsQhaMyvyF79eHaAinSZIYU52reFwX1KWzRfyQKzmkjBlKrDVX/RZTxPYehLjJlOPq7aMo+Cc8QbUqxBMWjG30NhP47r9lMCY0m2k2LaRnOdsfG5+Vic8ATped2fUb6jHIbWQ6gLSLZYzz8HwCOWp7myVzbVE+fi/zAI3v0RzYPaYENWhTerSSMHmn/Xg62qHbOgsZG93fj8RkELolvApJ1YETJjdagzMUkAWjtuDrLRApvDn1ETiT3HQb3AdrX2JZFeqfhcdsy6bLI3gnsDneiJiSfuJrsXHSVmcqbMN4D0BPf+GI0Rh+aPOvTOa4z0FUu4jbTMbwpnhaN9HB3U0fagaa5FjB98XsIEPcEAxTiyaFcJ8rELvc+FlJRlg9pjPSpPiOplBhcoNPdIrlu4UtfJcC4e+fl3FMfn2/d1FsYdLsBoFoh/nzqSNeXDFwVHsdLpKIzq3hg3V8oZvqKs+yOoqG+JuIkP6jwQiA== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(7416014)(82310400026)(1800799024)(376014)(23010399003)(3023799007)(11063799006)(18002099003)(22082099003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3J1/wrmUIRLpLt07nOKStEdnyWYsEg6dynzQEknHb1RDDQhIP7f0zv9XA0xcIeMbyZMMS5dGu4aeQqVzI7vfsmLW2e0B5zEKVvAmyA2v/93rZK2prCxF4L0mT/4pCRQi61NHWeR4pcwWYhPs68HyUDWX6L/6lXsovi/gtQzUBx0X1IRtXnNLXZbaryaheNWJxQO272pHS9KJ1L7NdwoZ063prRIG5qPzbBWbezQW5za/TSfec3bf3D1sNmh22oFujTpUkUnvTpm9I/0JpNK5SLuacIMeKbtfzNe4iRZlQYvk+ZpFJJRCFdINxpjlyquYCLRiVEROEkjEIhQUayi6+HLsKBiLb7S3M26CYbigrWSnMguZcHpH8WJvrqDVWTkul9qQI/mwq+FK+TS2YS8ims9Kyn0f35DIl3o7610nRDZ9DOKXqKMYagaJQ31/46i6 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jul 2026 04:08:04.8525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09545dc1-9ae6-416f-e46c-08ded8b8aeb5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6575 Both arm_smmu_cmdq_batch_submit() and arm_smmu_cmdq_batch_add_cmd_p() call arm_smmu_cmdq_issue_cmdlist() to flush batches. A future change will retry the issued commands on -EIO, using the arm_smmu_invs carried in the batch. So, a single hook point is preferred. Introduce an arm_smmu_cmdq_batch_issue() wrapper, so a retry logic will be simply filled into the wrapper. No functional changes. Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 4b4e8108d5944..6c099338a17ef 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -919,6 +919,14 @@ static void arm_smmu_cmdq_batch_init_cmd(struct arm_smmu_device *smmu, cmds->cmdq = arm_smmu_get_cmdq(smmu, cmd); } +static int arm_smmu_cmdq_batch_issue(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + bool sync) +{ + return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, + cmds->num, sync); +} + static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu, struct arm_smmu_cmdq_batch *cmds, struct arm_smmu_cmd *cmd) @@ -929,14 +937,12 @@ static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu, unsupported_cmd = !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd); if (force_sync || unsupported_cmd) { - arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, - cmds->num, true); + arm_smmu_cmdq_batch_issue(smmu, cmds, true); arm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd); } if (cmds->num == CMDQ_BATCH_ENTRIES) { - arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, - cmds->num, false); + arm_smmu_cmdq_batch_issue(smmu, cmds, false); arm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd); } @@ -952,8 +958,7 @@ static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu, static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, struct arm_smmu_cmdq_batch *cmds) { - return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, - cmds->num, true); + return arm_smmu_cmdq_batch_issue(smmu, cmds, true); } static void arm_smmu_page_response(struct device *dev, struct iopf_fault *unused, -- 2.43.0