From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8AABC43381 for ; Wed, 27 Mar 2019 19:03:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7B695206B7 for ; Wed, 27 Mar 2019 19:03:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389891AbfC0TDB (ORCPT ); Wed, 27 Mar 2019 15:03:01 -0400 Received: from foss.arm.com ([217.140.101.70]:59472 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389416AbfC0SNb (ORCPT ); Wed, 27 Mar 2019 14:13:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9E425A78; Wed, 27 Mar 2019 11:13:30 -0700 (PDT) Received: from [10.1.196.92] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 091A73F557; Wed, 27 Mar 2019 11:13:23 -0700 (PDT) Subject: Re: [RFC 0/7] cpuidle: Add poking mechanism to support non-IPI wakeup To: Leonard Crestez , "l.stach@pengutronix.de" , Richard Zhu Cc: Fabio Estevam , Cosmin Samoila , Robin Gong , Mircea Pop , Daniel Baluta , "catalin.marinas@arm.com" , Aisheng Dong , "shawnguo@kernel.org" , Robert Chiras , Anson Huang , Jun Li , Abel Vesa , "robh@kernel.org" , Zening Wang , dl-linux-imx , BOUGH CHEN , Horia Geanta , Peter Chen , Joakim Zhang , "rjw@rjwysocki.net" , Leo Zhang , Shenwei Wang , "linux-pm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Ranjani Vaidyanathan , Han Xu , "will.deacon@arm.com" , Iuliana Prodan , "sudeep.holla@arm.com" , "lorenzo.pieralisi@arm.com" , Jacky Bai , "linux-kernel@vger.kernel.org" , "mark.rutland@arm.com" , Peng Fan , "kernel@pengutronix.de" , Viorel Suman References: <1553692845-20983-1-git-send-email-abel.vesa@nxp.com> <1553701479.2561.38.camel@pengutronix.de> <564216aa-1144-71de-e887-00c58f466bf5@arm.com> <1553702767.2561.40.camel@pengutronix.de> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/03/2019 17:00, Leonard Crestez wrote: > On Wed, 2019-03-27 at 17:06 +0100, Lucas Stach wrote: >> Am Mittwoch, den 27.03.2019, 15:57 +0000 schrieb Marc Zyngier: >>> On 27/03/2019 15:44, Lucas Stach wrote: >>>> Am Mittwoch, den 27.03.2019, 13:21 +0000 schrieb Abel Vesa: >>>>> This work is a workaround I'm looking into (more as a background task) >>>>> in order to add support for cpuidle on i.MX8MQ based platforms. >>>>> >>>>> The main idea here is getting around the missing GIC wake_request signal >>>>> (due to integration design issue) by waking up a each individual core through >>>>> some dedicated SW power-up bits inside the power controller (GPC) right before >>>>> every IPI is requested for that each individual core. >>>> >>>> Just a general comment, without going into the details of this series: >>>> this issue is not only affecting IPIs, but also MSIs terminated at the >>>> GIC. Currently MSIs are terminated at the PCIe core, but terminating >>>> them at the GIC is clearly preferable, as this allows assigning CPU >>>> affinity to individual MSIs and lowers IRQ service overhead. >>>> >>>> I'm not sure what the consequences are for upstream Linux support yet, >>>> but we should keep in mind that having a workaround for IPIs is only >>>> solving part of the issue. >>> >>> If this erratum is affecting more than just IPIs, then indeed I don't >>> see how this patch series solves anything. >>> >>> But the erratum documentation seems to imply that only SGIs are >>> affected, and goes as far as suggesting to use an external interrupt >>> would solve it. How comes this is not the case? Or is it that anything >>> directly routed to a redistributor is also affected? This would break >>> LPIs (and thus MSIs) and PPIs (the CPU timer, among others). >>> >>> What is the *exact* status of this thing? I have the ugly feeling that >>> the true workaround is just to disable cpuidle. >> >> As far as I understand the erratum, the basic issue is that the GIC >> wake_request signals are not connected to the GPC (the CPU/peripheral >> power sequencer). The SPIs are routed through the GPC and thus are >> visible as wakeup sources, which is why the workaround of using an >> external SPI as wakeup trigger for the IPI works. > > We had a kernel workaround for IPIs in our internal tree for a long > time and I don't think we do anything special for PCI. Does PCI MSI > really bypass the GPC on 8mq? If you have an ITS, certainly. If you don't, it depends. MSIs can hit the distributor's MBI registers and generate non-wired SPIs, which I assume will bypass the GPC altogether. > Adding Richard/Jacky, they might know about this. > > This seems like something of a corner case to me, don't many imx boards > ship without PCI; especially for low-power scenarios? If required it > might be reasonable to add an additional workaround to disable all > cpuidle if pci msis are used. Establishing a link between cpuidle and PCI in the kernel would be pretty invasive, and that would come on top of what this series also mandates. At that level of apparent brokenness, it is far safer to get cpuidle out of the picture altogether, and I'd rather see these patches in a vendor tree (for once). Thanks, M. -- Jazz is not dead. It just smells funny...