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Mon, 24 Feb 2025 02:33:07 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51O2X68O004256 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Feb 2025 02:33:06 GMT Received: from [10.110.85.197] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 23 Feb 2025 18:33:05 -0800 Message-ID: <0b387a53-a67f-400d-b8a0-8c904496a558@quicinc.com> Date: Sun, 23 Feb 2025 18:33:05 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] drm/msm/dpu: enable CDM_0 for DPUs 5.x+ To: Dmitry Baryshkov , Rob Clark , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter CC: , , , References: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> <20250220-dpu-add-cdm-v2-2-77f5f0df3d9a@linaro.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20250220-dpu-add-cdm-v2-2-77f5f0df3d9a@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3GD14BWOHkiae9x-jYkXwfM72cntEPcK X-Proofpoint-GUID: 3GD14BWOHkiae9x-jYkXwfM72cntEPcK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-23_11,2025-02-20_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=770 priorityscore=1501 lowpriorityscore=0 adultscore=0 spamscore=0 malwarescore=0 bulkscore=0 mlxscore=0 suspectscore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502240018 On 2/19/2025 7:59 PM, Dmitry Baryshkov wrote: > Enable the CDM_0 block on DPU generations starting from 5.x as > documented in the vendor dtsi file. > > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 + > 11 files changed, 11 insertions(+) > Reviewed-by: Abhinav Kumar