Re: [PATCH v12 0/3] arm: dts: altera: add Draeger M48 CPU board

[Dinh Nguyen <dinguyen@kernel.org>]

On 10/16/26 07:34, Petko Manolov wrote:
> Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera
> SoCFPGA Cyclone V” board variant.  It has both (the SoC and FPGA) on the
> same carrier and they are cross-monitoring each other.  The SoCFPGA boots
> independently off qspi flash.
> 
> This is the SoCFPGA devicetree part.
> 
> in v12:
> 
>    - add proper compatible string to the mdio node;
> 
> in v11:
> 
>    - replace the ethphy compatible string;
> 
> and in v10:
> 
>    - add device_type back to the memory node;
>    - move the compatible string under the phy node;
> 
> news for v9:
> 
>    - remove the name property from the memory node;
>    - fix a typo in a comment;
>    - attached phy-specific skew properties to dedicated mdio phy sub-node;
>    - add Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> 
> now in v8:
> 
>    - modified draeger,m48 to draeger,socfpga-48 because it is more consistent;
>      with its other imx counterparts imx6q-m48 and imx6dl-m48;
>    - dropped gpio3 and gpio4 bindings;
> 
> new in v7:
> 
>    - replaced module with board as this seems to be confusing to some;
>    - add Acked-by: Conor Dooley <conor.dooley@microchip.com> tag;
> 
> Petko Manolov (3):
>    dt-bindings: vendor-prefixes: add Draeger AG
>    dt-bindings: arm: altera: add Draeger M48 dual-cpu board
>    arm: dts: altera: add Draeger M48 CPU Module
> 
>   .../devicetree/bindings/arm/altera.yaml       |   1 +
>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>   arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
>   .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 102 ++++++++++++++++++
>   4 files changed, 106 insertions(+)
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> 


Applied!

Thanks,
Dinh