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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b1f296c66sm375804566b.109.2024.10.28.06.15.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Oct 2024 06:15:23 -0700 (PDT) Message-ID: <0b5d01b6-988c-4d3c-b4dd-ee0afc288166@oss.qualcomm.com> Date: Mon, 28 Oct 2024 14:15:22 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] nvme-pci: Force NVME_QUIRK_SIMPLE_SUSPEND on Qualcomm hosts To: Christoph Hellwig Cc: Konrad Dybcio , Keith Busch , Jens Axboe , Sagi Grimberg , Bjorn Andersson , Marijn Suijten , linux-nvme@lists.infradead.org, linux-kernel@vger.kernel.org References: <20241024-topic-nvmequirk-v1-1-51249999d409@oss.qualcomm.com> <20241025113520.GA19521@lst.de> <0fac5de3-3f35-4fc2-bbdc-411dc1018a85@oss.qualcomm.com> <20241028091941.GA29461@lst.de> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241028091941.GA29461@lst.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: KF-IgiU6cpV75ecNvs9iMe7NrB1jxQ7Q X-Proofpoint-GUID: KF-IgiU6cpV75ecNvs9iMe7NrB1jxQ7Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 malwarescore=0 priorityscore=1501 phishscore=0 mlxscore=0 suspectscore=0 mlxlogscore=669 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280107 On 28.10.2024 10:19 AM, Christoph Hellwig wrote: > On Fri, Oct 25, 2024 at 05:30:05PM +0200, Konrad Dybcio wrote: >> (Un?)fortunately, said platforms use FDT, so we can't fix that in ACPI. > > Then generalize the acpi helper to a generic one checking ACPI and > DT and specify a proper DT binding. > > If th requirement to put all devices into D3 is a plaform propery > a specific driver is always the wrong place for it. > >> b) Adding such a property to the PCIe host node sounds a bit >> saner, but the NVMe code isn't aware of the RC. We could add >> something like: > > Again, this all belongs into core code. The nvme driver is just > a consumer of this information, just like for example the AHCI > driver. Alright, I'll try to pursue that angle instead, Konrad