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Tue, 16 Sep 2025 02:18:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFUTp4KmbKb6w4ICddFjxV1wTcHyF4t8EHj7cMp3vuJ2wqlH26j9yp2DgzTArzCXUUfH1i7TA== X-Received: by 2002:a17:903:166e:b0:265:44ae:d24 with SMTP id d9443c01a7336-26544ae0f0fmr109024895ad.43.1758014302506; Tue, 16 Sep 2025 02:18:22 -0700 (PDT) Received: from [10.218.33.29] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2663f6337b3sm56192015ad.102.2025.09.16.02.18.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Sep 2025 02:18:22 -0700 (PDT) Message-ID: <0b950a45-21e5-4c8d-bc76-1c801b86e2ef@oss.qualcomm.com> Date: Tue, 16 Sep 2025 14:47:53 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] bus: mhi: host: mhi_phc: Add support for PHC over MHI To: Jakub Kicinski , Krishna Chaitanya Chundru Cc: Manivannan Sadhasivam , Richard Cochran , mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, taniya.das@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com References: <20250818-tsc_time_sync-v1-0-2747710693ba@oss.qualcomm.com> <20250818-tsc_time_sync-v1-5-2747710693ba@oss.qualcomm.com> <20250821180247.29d0f4b3@kernel.org> Content-Language: en-US From: Imran Shaik In-Reply-To: <20250821180247.29d0f4b3@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=JO87s9Kb c=1 sm=1 tr=0 ts=68c92b5f cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=xLYDFgVRoUo0Dj3B0GAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: GAuWgcIyrv6bqgwLOzf9SwyjObqfelE8 X-Proofpoint-GUID: GAuWgcIyrv6bqgwLOzf9SwyjObqfelE8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTEzMDA0MCBTYWx0ZWRfX5r3XOqfgsyq8 NbURaO/RwKSSscxBriuBOjPURksmDzRjPKnpRHvkOjt3s2IliXDEHBdGdvDwfgLNQYWbvBlkWSf Bt3lIH7n9dCn2tAfeFQgyLufZIvvVHkwOhIUHl/3L69zX/wwMVmI75N+tD7/Sl8ov6JlUCse/Kl /qFsYzK8sL5VbKcQyicQHgrxjHsWD5Y/+XWD/N+u049LemhBkMYMa1Kmo7UWqTsuAB9H7glkld0 ZyNZaayIod6d1X8bJR/DGamBU38exIVHTEXrC5LYNMc4v2iBIvIBW7+Ahp7RBSet3elmg31YfeE q93gCRsfpQRi3a1eigU2yjR421icIatHZQaiOPWjAXI4WhsWSiUBjK/9K7kFxO6pUy3H99fPTI7 F28RzFiI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-16_02,2025-09-12_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509130040 On 8/22/2025 6:32 AM, Jakub Kicinski wrote: > On Mon, 18 Aug 2025 12:25:50 +0530 Krishna Chaitanya Chundru wrote: >> This patch introduces the MHI PHC (PTP Hardware Clock) driver, which >> registers a PTP (Precision Time Protocol) clock and communicates with >> the MHI core to get the device side timestamps. These timestamps are >> then exposed to the PTP subsystem, enabling precise time synchronization >> between the host and the device. > >> +static struct ptp_clock_info qcom_ptp_clock_info = { >> + .owner = THIS_MODULE, >> + .gettimex64 = qcom_ptp_gettimex64, >> +}; > > Yet another device to device clock sync driver. Please see the > discussion here: > https://lore.kernel.org/all/20250815113814.5e135318@kernel.org/ > I think we have a consensus within the community that we should > stop cramming random clocks into the PTP subsystem. > > Exporting read-only clocks from another processor is not what PTP > is for. Hi Jakub, Thank you for the review and for sharing the link to the ongoing discussion. I understand the concerns about using the PTP subsystem for read-only clocks. The idea behind this patch was to use a standard interface for syncing time between the host and device, and also to make use of existing tools like phc2sys from userspace. I have looked into the on going discussion you pointed, and we’re facing a similar challenge. Based on internal discussion with the PCIe team, we’ve confirmed that PCIe PTM isn’t applicable for this hardware use case. That said, since it seems the community prefers not to use PTP for such requirement, could you please suggest any other way to support this time sync requirement that would be acceptable upstream? Appreciate your guidance! Thanks, Imran