From: Paolo Bonzini <pbonzini@redhat.com>
To: "Dr. David Alan Gilbert" <dgilbert@redhat.com>,
Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>,
Thomas Gleixner <tglx@linutronix.de>,
bp@alien8.de, dwmw@amazon.co.uk, gregkh@linux-foundation.org,
pjt@google.com, mingo@kernel.org, linux-kernel@vger.kernel.org,
hpa@zytor.com, tim.c.chen@linux.intel.com,
torvalds@linux-foundation.org, peterz@infradead.org,
dave.hansen@intel.com, linux-tip-commits@vger.kernel.org
Subject: Re: [tip:x86/pti] x86/cpu/AMD: Use LFENCE_RDTSC instead of MFENCE_RDTSC
Date: Mon, 8 Jan 2018 18:01:36 +0100 [thread overview]
Message-ID: <0be27b7e-7285-b23b-7eda-55a70338d16c@redhat.com> (raw)
In-Reply-To: <20180108164803.GF2462@work-vm>
On 08/01/2018 17:48, Dr. David Alan Gilbert wrote:
>> If your hypervisor is lying to you about the primary family, then all
>> bets are off. I don't expect there will be any production systems doing
>> this.
> It's not that an unusual thing to do on qemu/kvm - to specify the lowest
> common denominator of the set of CPUs in your data centre (for any one
> vendor); it does tend to get some weird combinations.
Agreed. But on a hypervisor we pretty much know that:
- the MSR_AMD64_DE_CFG doesn't exist unless you have a fix
- setting the MSR_AMD64_DE_CFG bit to 1 if you have a fix can be done
independent of the family
So all KVM needs is a X86_FEATURE_LFENCE_SERIALIZE, it doesn't matter if
it's because of the family or because Linux has set MSR_F10H_DE_CFG.
The guest will either try setting the MSR bit and #GP, or it will find
it already set and do nothing.
Of course no code for this has been written yet.
Paolo
next prev parent reply other threads:[~2018-01-08 17:01 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-05 16:07 [PATCH v1 0/3] x86/cpu/AMD: Make LFENCE a serializing instruction on AMD Tom Lendacky
2018-01-05 16:07 ` [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction Tom Lendacky
2018-01-05 16:35 ` Brian Gerst
2018-01-05 16:36 ` Tom Lendacky
2018-01-06 21:05 ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-05 16:07 ` [PATCH v1 2/3] x86/cpu/AMD: Use LFENCE_RDTSC instead of MFENCE_RDTSC Tom Lendacky
2018-01-06 21:06 ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-08 10:08 ` Thomas Gleixner
2018-01-08 10:23 ` Woodhouse, David
2018-01-08 10:25 ` Thomas Gleixner
2018-01-08 10:40 ` Andrew Cooper
2018-01-08 11:10 ` Thomas Gleixner
2018-01-08 14:47 ` Tom Lendacky
2018-01-08 14:54 ` Andrew Cooper
2018-01-08 16:48 ` Dr. David Alan Gilbert
2018-01-08 17:01 ` Paolo Bonzini [this message]
2018-01-08 17:39 ` Tom Lendacky
2018-01-08 17:42 ` Paolo Bonzini
2018-01-17 17:21 ` Tom Lendacky
2018-01-17 17:53 ` Paolo Bonzini
2018-01-08 15:02 ` David Woodhouse
2018-01-08 15:15 ` Thomas Gleixner
2018-01-08 17:31 ` Tom Lendacky
2018-01-08 20:57 ` Thomas Gleixner
2018-01-05 16:08 ` [PATCH v1 3/3] x86/msr: Remove now unused definition of MFENCE_RDTSC feature Tom Lendacky
2018-01-06 21:06 ` [tip:x86/pti] " tip-bot for Tom Lendacky
2018-01-05 16:56 ` [PATCH v1 0/3] x86/cpu/AMD: Make LFENCE a serializing instruction on AMD Borislav Petkov
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