Re: [PATCH v4 2/3] migration: qm updates BAR configuration

[liulongfang <liulongfang@huawei.com>]

On 2025/6/24 15:06, Shameerali Kolothum Thodi wrote:
> 
> 
>> -----Original Message-----
>> From: liulongfang <liulongfang@huawei.com>
>> Sent: Tuesday, June 10, 2025 7:33 AM
>> To: alex.williamson@redhat.com; jgg@nvidia.com; Shameerali Kolothum
>> Thodi <shameerali.kolothum.thodi@huawei.com>; Jonathan Cameron
>> <jonathan.cameron@huawei.com>
>> Cc: kvm@vger.kernel.org; linux-kernel@vger.kernel.org;
>> linuxarm@openeuler.org; liulongfang <liulongfang@huawei.com>
>> Subject: [PATCH v4 2/3] migration: qm updates BAR configuration
>>
>> On the new hardware platform, the configuration region for the
>> live migration function of the accelerator device is no longer
>> placed in the VF, but is instead placed in the PF.
>>
>> Therefore, the configuration region of the live migration function
>> needs to be opened when the QM driver is loaded. When the QM driver
>> is uninstalled, the driver needs to clear this configuration.
>>
>> Signed-off-by: Longfang Liu <liulongfang@huawei.com>
>> ---
>>  drivers/crypto/hisilicon/qm.c | 29 +++++++++++++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
>> index d3f5d108b898..0a8888304e15 100644
>> --- a/drivers/crypto/hisilicon/qm.c
>> +++ b/drivers/crypto/hisilicon/qm.c
>> @@ -242,6 +242,9 @@
>>  #define QM_QOS_MAX_CIR_U		6
>>  #define QM_AUTOSUSPEND_DELAY		3000
>>
>> +#define QM_MIG_REGION_SEL		0x100198
>> +#define QM_MIG_REGION_EN		0x1
>> +
>>   /* abnormal status value for stopping queue */
>>  #define QM_STOP_QUEUE_FAIL		1
>>  #define	QM_DUMP_SQC_FAIL		3
>> @@ -3004,11 +3007,36 @@ static void qm_put_pci_res(struct hisi_qm *qm)
>>  	pci_release_mem_regions(pdev);
>>  }
>>
>> +static void hisi_mig_region_clear(struct hisi_qm *qm)
>> +{
>> +	u32 val;
>> +
>> +	/* Clear migration region set of PF */
>> +	if (qm->fun_type == QM_HW_PF && qm->ver > QM_HW_V3) {
> 
> Is this going to be same for all future hardware's like OM_HW_V5, OM_HW_V6 etc?
> Otherwise it is better you make it specific to OM_HW_V4. I think
> the above checking  is repeated throughout this series and there is no guarantee
> that future hardware will have the same changes only. So better make it specific.
>

We confirmed with hardware team that the subsequent implementations will continue
to use this approach.

Thanks.
Longfang.

> Thanks,
> Shameer
> 
> 
>> +		val = readl(qm->io_base + QM_MIG_REGION_SEL);
>> +		val &= ~BIT(0);
>> +		writel(val, qm->io_base + QM_MIG_REGION_SEL);
>> +	}
>> +}
>> +
>> +static void hisi_mig_region_enable(struct hisi_qm *qm)
>> +{
>> +	u32 val;
>> +
>> +	/* Select migration region of PF */
>> +	if (qm->fun_type == QM_HW_PF && qm->ver > QM_HW_V3) {
>> +		val = readl(qm->io_base + QM_MIG_REGION_SEL);
>> +		val |= QM_MIG_REGION_EN;
>> +		writel(val, qm->io_base + QM_MIG_REGION_SEL);
>> +	}
>> +}
>> +
>>  static void hisi_qm_pci_uninit(struct hisi_qm *qm)
>>  {
>>  	struct pci_dev *pdev = qm->pdev;
>>
>>  	pci_free_irq_vectors(pdev);
>> +	hisi_mig_region_clear(qm);
>>  	qm_put_pci_res(qm);
>>  	pci_disable_device(pdev);
>>  }
>> @@ -5630,6 +5658,7 @@ int hisi_qm_init(struct hisi_qm *qm)
>>  		goto err_free_qm_memory;
>>
>>  	qm_cmd_init(qm);
>> +	hisi_mig_region_enable(qm);
>>
>>  	return 0;
>>
>> --
>> 2.24.0
> 
> .
>