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Thu, 05 Sep 2024 04:56:57 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4854utwO007152 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 5 Sep 2024 04:56:55 GMT Received: from [10.233.21.53] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Sep 2024 21:56:51 -0700 Message-ID: <0c7790b8-fcfc-43cc-a2af-5096522b1dec@quicinc.com> Date: Thu, 5 Sep 2024 12:56:49 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 18/19] arm64: dts: qcom: add initial support for QCS8300 DTSI To: Krzysztof Kozlowski , Bjorn Andersson , Mathieu Poirier , "Rob Herring" , Conor Dooley , "Bartosz Golaszewski" CC: , , , , , , "Zhenhua Huang" , Xin Liu , "Kyle Deng" , Tingguo Cheng References: <20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com> <20240904-qcs8300_initial_dtsi-v1-18-d0ea9afdc007@quicinc.com> Content-Language: en-US From: Jingyi Wang In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4xHw51o4RZeAhvOIFvs4YUVISUWlqqPZ X-Proofpoint-ORIG-GUID: 4xHw51o4RZeAhvOIFvs4YUVISUWlqqPZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-05_04,2024-09-04_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2409050034 On 9/4/2024 5:41 PM, Krzysztof Kozlowski wrote: > On 04/09/2024 10:33, Jingyi Wang wrote: >> Add initial DTSI for QCS8300 SoC. >> >> This revision brings support for: >> - CPUs with cpu idle >> - interrupt-controller with PDC wakeup support >> - gcc >> - TLMM >> - interconnect >> - qup with uart >> - smmu >> - pmic >> - ufs >> - ipcc >> - sram >> - remoteprocs including ADSP,CDSP and GPDSP >> >> [Zhenhua: added the smmu node] >> Co-developed-by: Zhenhua Huang >> Signed-off-by: Zhenhua Huang >> [Xin: added ufs/adsp/gpdsp nodes] >> Co-developed-by: Xin Liu >> Signed-off-by: Xin Liu >> [Kyle: added the aoss_qmp node] >> Co-developed-by: Kyle Deng >> Signed-off-by: Kyle Deng >> [Tingguo: added the pmic nodes] >> Co-developed-by: Tingguo Cheng >> Signed-off-by: Tingguo Cheng >> [Raviteja: added interconnect nodes] >> Co-developed-by: Raviteja Laggyshetty >> Signed-off-by: Raviteja Laggyshetty >> Signed-off-by: Jingyi Wang >> --- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1282 +++++++++++++++++++++++++++++++++ >> 1 file changed, 1282 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> new file mode 100644 >> index 000000000000..244fa8bf97d9 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> @@ -0,0 +1,1282 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +/ { >> + interrupt-parent = <&intc>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + clocks { >> + sleep_clk: sleep-clk { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <32000>; > > Are you sure that sleep clock is physically part of the SoC? > Have checked that and will move it to board.dts >> + }; >> + }; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + > > ... > >> + >> + soc: soc@0 { >> + compatible = "simple-bus"; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0 0 0 0 0x10 0>; > > ranges follow compatible, so it is the second property. > > Well noted, thanks for review. > > Best regards, > Krzysztof > Thanks, Jingyi