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Fri, 20 Dec 2024 11:29:05 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BKBT46d028128 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Dec 2024 11:29:04 GMT Received: from [10.152.195.140] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 20 Dec 2024 03:28:56 -0800 Message-ID: <0c7c1979-6fc3-4059-bf08-c94f6424b1dd@quicinc.com> Date: Fri, 20 Dec 2024 16:58:53 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] arm64: dts: qcom: ipq5424: Add PCIe PHYs and controller nodes To: Konrad Dybcio , , , , , , , , , , , , , , , , CC: , References: <20241213134950.234946-1-quic_mmanikan@quicinc.com> <20241213134950.234946-4-quic_mmanikan@quicinc.com> <69dffe54-939d-47c3-b951-4a4dea11eae0@oss.qualcomm.com> <08fbde92-a827-4270-a143-cca56a274e6c@quicinc.com> <71d2135f-664a-465d-bc1f-051cc07c8537@oss.qualcomm.com> Content-Language: en-US From: Manikanta Mylavarapu In-Reply-To: <71d2135f-664a-465d-bc1f-051cc07c8537@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZzBnjh2nN8OwLgERvuK6_pJLmUbpRQ1g X-Proofpoint-ORIG-GUID: ZzBnjh2nN8OwLgERvuK6_pJLmUbpRQ1g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 clxscore=1015 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412200095 On 12/20/2024 3:18 PM, Konrad Dybcio wrote: > On 20.12.2024 7:42 AM, Manikanta Mylavarapu wrote: >> >> >> On 12/13/2024 8:36 PM, Konrad Dybcio wrote: >>> On 13.12.2024 2:49 PM, Manikanta Mylavarapu wrote: >>>> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices >>>> found on IPQ5424 platform. The PCIe0 & PCIe1 are 1-lane Gen3 >>>> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. >>>> >>>> Signed-off-by: Manikanta Mylavarapu >>>> --- > > [...] > >>>> tlmm: pinctrl@1000000 { >>>> compatible = "qcom,ipq5424-tlmm"; >>>> @@ -168,11 +261,11 @@ gcc: clock-controller@1800000 { >>>> reg = <0 0x01800000 0 0x40000>; >>>> clocks = <&xo_board>, >>>> <&sleep_clk>, >>>> + <&pcie0_phy>, >>>> + <&pcie1_phy>, >>>> <0>, >>> >>> This leftover zero needs to be removed too, currently the wrong >>> clocks are used as parents >>> >> >> Hi Konrad, >> >> The '<0>' entry is for "USB PCIE wrapper pipe clock source". >> And, will update the pcie entries as follows >> <&pcie0_phy GCC_PCIE0_PIPE_CLK> >> <&pcie1_phy GCC_PCIE1_PIPE_CLK> >> <&pcie2_phy GCC_PCIE2_PIPE_CLK> >> <&pcie3_phy GCC_PCIE3_PIPE_CLK> >> >> Please correct me if i am wrong. > > The order of these is fixed by the first enum in > drivers/clk/qcom/gcc-ipq5424.c. The <0> entry must be at the end of > the clocks list for it to do what you want it to. > I understand your point. I will move the <0> entry to the end and incorporate this change in the next version. Thanks & Regards, Manikanta.